參數(shù)資料
型號： HYB18T512800AF-37
廠商： INFINEON TECHNOLOGIES AG
英文描述： 512-Mbit Double-Data-Rate-Two SDRAM
中文描述： 512兆雙數(shù)據(jù)速率2內(nèi)存
文件頁數(shù)： 59/96頁
文件大?。?/td> 1571K
代理商： HYB18T512800AF-37
HYB18T512[400/800/160]A[C/F]–[3.7/5]
512-Mbit Double-Data-Rate-Two SDRAM
Functional Description
Data Sheet
59
Rev. 1.13, 2004-05
09112003-SDM9-IQ3P
Figure 53
Self Refresh Timing
Note:
1. Device must be in the “All banks idle” state before
entering Self Refresh mode.
2.
t
XSRD
(
≥
200
t
CK
) has to be satisfied for a Read or a Read
with Auto-Precharge command.
3. t
XSNR
has to be satisfied for any command except a
Read or a Read with Auto-Precharge command
4. Since CKE is an SSTL input,
V
REF
must be
maintained during Self Refresh.
2.10
Power-Down
Power-down is synchronously entered when CKE is
registered low, along with NOP or Deselect command.
CKE is not allowed to go low while mode register or
extended mode register command time, or read or write
operation is in progress. CKE is allowed to go low while
any other operation such as row activation, Precharge,
Auto-Precharge or Auto-Refresh is in progress, but
power-down
I
DD
specification will not be applied until
finishing those operations.
The DLL should be in a locked state when power-down
is entered. Otherwise DLL should be reset after exiting
power-down mode for proper read operation. DRAM
design guarantees it’s DLL in a locked state with any
CKE intensive operations as long as DRAM controller
complies with DRAM specifications.
If power-down occurs when all banks are precharged,
this mode is referred to as Precharge Power-down; if
power-down occurs when there is a row active in any
bank, this mode is referred to as Active Power-down.
For Active Power-down two different power saving
modes can be selected within the MRS register,
address bit A12. When A12 is set to “l(fā)ow” this mode is
referred as “standard active power-down mode” and a
fast power-down exit timing defined by the
t
XARD
timing
parameter can be used. When A12 is set to “high” this
mode is referred as a power saving “l(fā)ow power active
power-down mode”. This mode takes longer to exit
from the power-down mode and the
t
XARDS
timing
parameter has to be satisfied.
Entering power-down deactivates the input and output
buffers, excluding CK, CK, ODT and CKE. Also the DLL
is disabled upon entering Precharge Power-down or
slow exit active power-down, but the DLL is kept
enabled during fast exit active power-down. In power-
down mode, CKE low and a stable clock signal must be
maintained at the inputs of the DDR2 SDRAM, and all
other input signals are “Don’t Care”. Power-down
duration is limited by 9 times
t
REFI
of the device.
The power-down state is synchronously exited when
CKE is registered high (along with a NOP or Deselect
command). A valid, executable command can be
applied with power-down exit latency,
t
XP
,
t
XARD
or
t
XARDS
, after CKE goes high. Power-down exit latencies
are defined in
Table 40
.
CK/CK
T1
T3
T2
CK/CK may
be halted
CK/CK must
be stable
CKE
>=tXSRD
>= tXSNR
Tn
Tr
Tm
T5
T4
tRP
tis
tAOFD
CMD
Self Refresh
Entry
NOP
Non-Read
Command
Read
Command
T0
tis
tis
ODT
tCKE
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