參數(shù)資料
型號(hào)： HB52RD168DB
廠商： Hitachi,Ltd.
英文描述： 128 MB Unbuffered SDRAM S.O.DIMM(128MB 未緩沖同步DRAM DIMM)
中文描述： 128 MB的無(wú)緩沖內(nèi)存的SODIMM（128MB的未緩沖同步的DRAM內(nèi)存）
文件頁(yè)數(shù)： 21/67頁(yè)
文件大?。?/td> 623K
代理商： HB52RD168DB
HB52RD168DB-D
21
Pin Functions
CK0/CK1 (input pin):
CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0
(input pin):
When
S
is Low, the command input cycle becomes valid. When
S
is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE
,
CE
and
W
(input pins):
Although these pin names are the same as those of conventional DRAM
modules, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins):
Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9) is determined by A0 to A9 level at the
read or write command cycle CK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
A12/A13 (BA) is precharged.
A12/A13 (input pin):
A12/A13 is a bank select signal (BA). The memory array is divided into bank0,
bank1, bank2 and bank3, If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is
Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is
HIgh, bank3 is selected.
CKE0 (input pin):
This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down
and clock suspend modes.
DQMB0 to DQMB7 (input pins):
Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is
Low, the data is written.
DQ0 to DQ63 (DQ pins):
Data is input to and output from these pins.
V
CC
(power supply pins):
3.3 V is applied.
V
SS
(power supply pins):
Ground is connected.
相關(guān)PDF資料
PDF描述
HB52RD328DC 256 MB Unbuffered SDRAM S.O.DIMM(256 MB 未緩沖同步DRAM S.O.DIMM)
HB52RF1289E2-75B x72 SDRAM Module
HB52RF1289E2 1 GB Registered SDRAM DIMM 128-Mword 】 72-bit, 133 MHz Memory Bus, 2-Bank Module (36 pcs of 64 M 】 4 Components) PC133 SDRAM
HB52RF1289E2 1 GB Registered SDRAM DIMM(1GB 寄存同步DRAM DIMM)
HB52RF329E2 256 MB Registered SDRAM DIMM(256 MB 寄存同步DRAM DIMM)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HB52RD168DB-A6F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52RD168DB-A6FL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52RD168DB-B6F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52RD168DB-B6FL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
HB52RD168GB-A6F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*