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參數資料
| 型號： | GS1503-CFZ |
| 廠商： | Gennum Corporation |
| 元件分類： | Codec |
| 英文描述： | HD EMBEDDED AUDIO CODEC |
| 中文描述： | 高清嵌入式音頻編解碼 |
| 文件頁數： | 67/83頁 |
| 文件大?。?/td> | 815K |
| 代理商： | GS1503-CFZ |
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15879 - 4
67 of 83
G
RSV
Not used.
02F
7-3
-
0
CTRONA
Ch1-4 audio control packet demultiplex enable.
When set HIGH, the audio control packets in the
Luma channel of the video data stream for audio
channels 1 to 4 will be demultiplexed.
2
R/W
1
CTRIDA[1:0]
Ch1-4 audio control packet DID setting. Designates
the audio control packet DID for audio channels 1
to 4.
See Table 13
. The default setting is audio
group 1.
1-0
R/W
11b
AF_NOA[8:0]
Ch1-4 audio frame number. Designates the audio
frame number for audio channels 1 to 4.
030
031
0
7-0
R/W
0
RATEA[2:0]
Ch1-4 sampling frequency. Designates the audio
sampling frequency for audio channels 1 to 4, taken
from the RATE word of the audio control packet as
defined in SMPTE 299M.
032
3-1
R/W
0
ASXA
Ch1-4 synchronization. When set HIGH, the "asx" bit
of the audio control packet RATE word designates
audio channels 1 to 4 as asynchronous, as per
SMPTE 299M. When set LOW, the "asx" bit of the
audio control packet RATE word designates
synchronous audio.
0
R/W
0
DEL1-2A[25:0]
Ch1/2 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 1 and 2.
033
034
035
036
1-0
7-0
7-0
7-0
R/W
0
DEL3-4A[25:0]
Ch3/4 delay data. Designates the accumulated
audio processing delay relative to video for audio
channels 3 and 4.
037
038
039
03A
1-0
7-0
7-0
7-0
R/W
0
RSRVA[17:0]
Ch1-4 reserve words. Designates the value set in
the RSRV words of the audio control packet for
audio channels 1 to 4, as per SMPTE 299M.
03B
03C
03D
1-0
7-0
7-0
R/W
0
Packet
Delete
RSV
Not used.
040
7-2
-
0
ANCI
Ancillary data delete. When set HIGH, all ancillary
data packets ("DEL_SEL" is LOW) or ancillary data
packets with DIDs designated in Host Interface
registers 041h and 042h ("DEL_SEL" is HIGH) are
removed from the video signal. The ancillary data
packets are replaced with blanking codes. The data
contained in the packets are output at the
corresponding pins. When set LOW, all ancillary
data packets remain in the video signal.
NOTE: The status of the ANCI external pin is not
updated in this register. The value programmed in
this register is logical OR'd with the ANCI external
pin setting
1
R/W
0
DEL_SEL
Ancillary data delete mode select. When set HIGH,
individual audio groups can be deleted from the
video signal by programming Host Interface
register 041h. When set LOW, all ancillary data
packets are deleted from the video signal.
0
R/W
0
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
NAME
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
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