
15879 - 4
11 of 83
G
79
AOUT7/8
O
Audio signal output for channels 7 and 8. The AES/EBU digital audio output is bi-phase
mark encoded. In both non-AES/EBU modes, the output is not bi-phase mark encoded.
85
DEC_MODE
I
Demultiplex Mode select. Valid in Demultiplex Mode only. When set HIGH, the GS1503
requires a 48kHz word clock input at WCINA and WCINB. This word clock must be
synchronous to the word clock used to embed the audio data. The embedded audio
clock phase information in the ancillary data packet will be ignored.
See Section 2-11.
87
VCLK
I
Video clock signal input.
81, 82, 83,
89, 94, 93,
92, 91, 90
CPUADR[8:0]
I
Host Interface address bus. CPUADR[8] is the MSB and CPUADR[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUADR[1:0] are used as the Host
Interface control bus.
See Table 1.
103, 102,
101, 100,
99, 98, 96,
95
CPUDAT[7:0]
I/O
Host Interface data bus. CPUDAT[7] is the MSB and CPUDAT[0] is the LSB.
In Host Interface Mode B (CPU_SEL set LOW), CPUDAT[7:0] are used as the Host
Interface address and data bus.
105
CPUCS
I
Chip select for Host Interface. Active LOW.
106
CPURE
I
Read enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is not used.
107
CPUWE
I
Write enable for Host Interface. Active LOW. In Host Interface Mode B (CPU_SEL set
LOW), this input is used as the Host Interface control enable.
110, 111,
112, 114,
115, 116,
118, 119,
120, 122,
123, 124,
126, 127,
128, 130,
131, 132,
134, 135
VIN[19:0]
I
Parallel digital video signal input. VIN[19] is the MSB and VIN[0] is the LSB.
136
CPU_SEL
I
Host Interface mode select. When set HIGH, the GS1503 is configured for Host Interface
Mode A. When set LOW, the GS1503 is configured for Host Interface Mode B.
137, 138
AM[1:0]
I
Audio format select. In Multiplex Mode, AM[1:0] indicates the input audio data format.
In Demultiplex Mode, AM[1:0] indicates the output audio data format. AM[1] is the MSB
and AM[0] is the LSB.
See Tables 3 and 11.
139, 140,
141, 142
VM[3:0]
I
Video standard select. VM[3] is the MSB and VM[0] is the LSB.
See Table 2 or 10.
143
RESET
I
Device reset. Active LOW.
PIN DESCRIPTIONS (Continued)
NUMBER
SYMBOL
TYPE
DESCRIPTION