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2.6.2 Digital Audio Output Timing
2.6.2.1 AES/EBU Format Output
A 6.144MHz (128fs) audio clock must be supplied to the
ACLKA and ACLKB inputs. ACLKA is used to clock AES/
EBU digital audio signal for channels 1 to 4 (AOUT1/2 and
AOUT3/4). ACLKB is used to clock AES/EBU digital audio
signal for channels 5 to 8 (AOUT5/6 and AOUT7/8). In AES/
EBU output mode, the audio word clock inputs WCINB and
WCINB should be grounded.
See Figure 37 for timing
.
The user can access the Audio Channel Status Block
information via the AUDIO_CS[183:0] bits in Host Interface
registers 058h to 06Eh. To read the Audio Channel Status
information, the CS_MODE bit 3 of Host Interface register
06Fh should be set HIGH. The embedded audio channel
from which the Channel Status information is to be
extracted is set in the CH_SEL[2:0] bits 2-0 of Host
Interface register 06Fh. The CH_SEL[2:0] setting for audio
channel 1 is 000b, through to 111b for channel 8. The
CS_RQST bit must be set HIGH to begin the process of
extracting the Audio Channel Status information. Once
extracted, the GS1503 will set CS_WEND bit HIGH and the
user can access the data for Host Interface registers 058h
to 06Eh.
When CS_MODE is set LOW, the Audio Channel Status
information in the AES/EBU audio outputs will be replaced
with data programmed in the AUDIO_CS[183:0] bits of Host
Interface registers 058h to 06Eh.
Fig. 37 AES/EBU Audio Output Configuration and Timing
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
CS_WEND
Audio Channel Status write flag
(1: Data ready)
06F
5
-
0
CS_RQST
Audio Channel Status request
(1: enable)
4
1
0
CS_MODE
0: Audio Channel Status replace
1: Audio Channel Status demultiplex
3
1
0
CH_SEL[2:0]
Audio Channel Status select
2-0
-
000b
Y/Cb/Cr[19:0]
VIN[19:0]
AOUT5/6
GS1503
AOUT1/2
AOUT3/4
AOUT7/8
ACLKA
ACLKB
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
6.144MHz (128 fs)
6.144MHz (128 fs)
ACLKA/B
AOUT1/2, AOUT3/4
AOUT5/6, AOUT7/8
6.144MHz