參數(shù)資料
型號(hào)： GS1503-CFZ
廠商： Gennum Corporation
元件分類： Codec
英文描述： HD EMBEDDED AUDIO CODEC
中文描述： 高清嵌入式音頻編解碼
文件頁(yè)數(shù)： 58/83頁(yè)
文件大小： 815K
代理商： GS1503-CFZ
15879 - 4
58 of 83
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2.10.2 Audio Group Designation Ancillary Data Deletion
When the ANCI bit 1 of Host Interface register 040h is set
HIGH, and DEL_SEL bit 0 of Host Interface register 040h is
HIGH, only audio data and control packets which are
designated in Host Interface registers 041h will be deleted.
To delete the arbitrary data packets, the corresponding DID
must be set in the NDID[7:0] Host Interface register 042h.
2.11 DEMULTIPLEX MODE WITH WORD CLOCK INPUT
Some commercially available HD audio embedding
modules do not encode the audio word clock phase
information correctly in the CLK words of the audio data
packet. If this clock information is not correctly encoded,
the GS1503 will not output the audio data correctly. Also,
the GS1503 will be unable to reproduce the 48kHz audio
word clock (fs) at the WCOUTA and WCOUTB pins in serial
audio output modes.
If the GS1503 is to be used in conjunction with a HD audio
module, which encodes audio clock phase information
incorrectly, the DEC_MODE external pin or DECMODE bit 2
of Host Interface register 01Eh must be set HIGH. When
HIGH, an audio word clock synchronous to the original
word clock used for embedding must be input at the
WCINA and WCINB pins. Figure 43 shows a system
example.
When the embedded clock phase data for audio channel 1
to 4 is detected as being in error, the MUXERRA bit 0 of
Host Interface register 01Eh will be set HIGH. Similarly,
when the embedded clock phase data for audio channel 5
to 8 is detected as being in error, the MUXERRB bit 1 of
Host Interface register 01Eh will be set HIGH
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
ANCI
Ancillary data packet delete (1: Deletion enabled)
040
1
1
0
DEL_SEL
Ancillary data packet delete mode select
(0: Entire data delete; 1: Group designated data delete)
0
1
0
ADPG4_DEL
Audio group 4 data packet delete (1: Delete)
041
7
-
0
ADPG3_DEL
Audio group 3 data packet delete (1: Delete)
6
-
0
ADPG2_DEL
Audio group 2 data packet delete (1: Delete)
5
-
0
ADPG1_DEL
Audio group 1 data packet delete (1: Delete)
4
-
0
ACPG4_DEL
Audio group 4 control packet delete (1: Delete)
3
-
0
ACPG3_DEL
Audio group 3 control packet delete (1: Delete)
2
-
0
ACPG2_DEL
Audio group 2 control packet delete (1: Delete)
1
-
0
ACPG1_DEL
Audio group 1 control packet delete (1: Delete)
0
-
0
NDID[7:0]
Arbitrary packet DID delete setting
042
7-0
-
0
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
DECMODE
Demultiplex Mode with word clock input enable
(1: Enabled)
01E
2
1
0
MUXERRB
Ch5-8 embedded clock phase information error detect
(1: Detected)
1
-
0
MUXERRA
Ch1-4 embedded clock phase information error detect
(1: Detected)
0
-
0
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