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參數資料
| 型號： | GS1503-CFZ |
| 廠商： | Gennum Corporation |
| 元件分類： | Codec |
| 英文描述： | HD EMBEDDED AUDIO CODEC |
| 中文描述： | 高清嵌入式音頻編解碼 |
| 文件頁數： | 32/83頁 |
| 文件大?。?/td> | 815K |
| 代理商： | GS1503-CFZ |
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1.11 ARBITRARY DATA PACKETS
The GS1503 can multiplex arbitrary data packets according
to SMPTE 291M. Typically, this consists of linear time code
(LTC), vertical interval time code (VITC) or other user data,
which is multiplexed once per video field. The GS1503 has
two modes in which arbitrary data can be multiplexed into
the Luma channel of the video data stream. A maximum of
255 user data words can be multiplexed in one packet.
Figure 29 shows the structure of the arbitrary data packet.
NOTE: Arbitrary data packets will not be multiplexed in the
two lines following the video switching point (see Section
1.8).
Fig. 29 Arbitrary Data Packet Structure
1.11.1 Arbitrary Data Multiplexing In External Pin Mode
This is the default mode for multiplexing arbitrary data
packets. The GS1503 will set the PKTENO external pin
HIGH when arbitrary data can be input to the device. Two
VCLK cycles after PKTENO goes HIGH, the user should set
the PKTEN arbitrary packet enable pin HIGH. Two VCLK
cycles after PKTEN is set HIGH, arbitrary data can be input
at the PKT[7:0] bus. See Figure 30 for timing.
The user is required to enter the following arbitrary data:
Data ID (DID), Secondary Data ID (SDID), Data Count (DC)
and User Data Words (UDW: maximum of 255), via the
PKT[7-0] pins. This GS1503 automatically generates the
Ancillary Data Flag (ADF), Checksum (CS) and bit 8 (Parity
Bit) and bit 9 (Not bit 8).
The PKTENO pin will be set HIGH on all video lines except
the two lines following the video switching point. For
example, with the default setting of line 7 field 1, PKTENO
will not be set HIGH on lines 8 and 9. The switching point is
set in the SW_LNA[12:0] and SW_LNB[12:0] Host Interface
registers for field 1 and field 2 respectively.
See Section 1-8.
Fig. 30 Arbitrary Data Packet Input Timing Diagram
A
User Data Words
MSB
D
S
D
U
C
Contents set in Host Interface registers
U
U
U
U
U
U
U
LSB
Not b8
Parity bit
Y/Cb/ Cr[19:0]
VIN[19:0]
GS1503
PKTENO
PKTEN
PKT[7:0]
Arbitrary Data Packet Timing
Arbitrary Data Input Enable
Arbitrary Data
VCLK
PKT[7:0]
2 CLKs
2 CLKs
2 CLKs
2 CLKs
Arbitrary Data
PKTENO
PKTEN
Automatically generated by the GS1503
U
U
U
U
U
C
U
U
U
U
D
S
D
A
A
A
Arbitrary
Packet
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|---|---|
| GS1508-CKAE3 | HDTV Cable Driver |
| GS1508-CTAE3 | HDTV Cable Driver |
| GS1511-CQR | HD-LINX -TM GS1511 HDTV Serial Digital Formatter |
| GS1511-CQRE3 | HD-LINX -TM GS1511 HDTV Serial Digital Formatter |
| GS1524A | GS1524A HD-LINX-RII Adaptive Cable Equalizer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| GS1504 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Adaptive Equalizer |
| GS1504_04 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Adaptive Equalizer |
| GS1504-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1504-CKDE3 | 制造商:Gennum Corporation 功能描述:High Performance Cable Equalizer 16-Pin SOIC N |
| GS1504-CTD | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Adaptive Equalizer |
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