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參數(shù)資料
| 型號： | GS1503-CFZ |
| 廠商： | Gennum Corporation |
| 元件分類： | Codec |
| 英文描述： | HD EMBEDDED AUDIO CODEC |
| 中文描述： | 高清嵌入式音頻編解碼 |
| 文件頁數(shù)： | 61/83頁 |
| 文件大?。?/td> | 815K |
| 代理商： | GS1503-CFZ |
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15879 - 4
61 of 83
G
LN_INS
Line insertion enable. When set HIGH, the GS1503
will insert line numbers into the video data stream.
When set LOW, existing line numbers will remain in
the output video stream.
1
R/W
1
TRS_INS
TRS insertion enable. When set HIGH, the GS1503
will insert TRS codes into the video data stream.
When set LOW, existing TRS codes will remain in
the output video stream.
0
R/W
1
Audio
AM_SEL
Audio input format (external pin/register)
configuration select. When set LOW, the audio input
format is configured via the AM[1:0] pins. When set
HIGH, the audio input format is configured via the
"AM[1:0]" bits.
010
7
R/W
0
RSV
Not used.
6-2
-
0
AM[1:0]
Audio input format select.
See Table 11
. Valid when
"AM_SEL" is HIGH.
1-0
R/W
0
RSV
Not used.
01E
7-3
-
0
DECMODE
Demultiplex Mode select. When set HIGH, the
GS1503 requires a 48kHz word clock input at
WCINA and WCINB. This word clock must be
synchronous to the word clock used to embed the
audio data. The embedded clock information in the
audio data packet will be ignored.
See Section 2-11.
NOTE: The status of the DEC_MODE external pin is
not updated in this register. The value programmed
in this register is logical OR'd with the DEC_MODE
external pin setting.
2
R/W
0
MUXERRB
Ch5-8 audio sample clock error. When set HIGH,
the GS1503 is unable to recover the audio clock
phase data in the embedded audio data packet for
audio channels 5 to 8.
See Section 2-11.
1
R
0
MUXERRA
Ch1-4 audio sample clock error. When set HIGH,
the GS1503 is unable to recover the audio clock
phase data in the embedded audio data packet for
audio channels 1 to 4.
See Section 2-11.
0
R
0
Audio
Channel
Status
Block
AUDIO_CS[7:0]
:
AUDIO_CS
[183:176]
Audio Channel Status. When "CS_MODE" is set
HIGH, the 23 8-bit bytes of the Audio Channel
Status Block, as defined in AES3-1992, are
available in these registers. Valid in both AES/EBU
and serial audio modes.
When "CS_MODE" is set LOW, the Audio Channel
Status information in the AES/EBU audio outputs will
be replaced with data programmed in these
registers. Valid only in AES/EBU audio mode.
058
:
06E
7-0
:
7-0
R
0
RSV
Not used
06F
7-6
-
0
Table 14: Demultiplex Mode Host Interface Registers (Continued)
CONTROL
ITEM
NAME
DESCRIPTION
ADDRESS
BIT
R/W
DEFAULT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GS1508-CKAE3 | HDTV Cable Driver |
| GS1508-CTAE3 | HDTV Cable Driver |
| GS1511-CQR | HD-LINX -TM GS1511 HDTV Serial Digital Formatter |
| GS1511-CQRE3 | HD-LINX -TM GS1511 HDTV Serial Digital Formatter |
| GS1524A | GS1524A HD-LINX-RII Adaptive Cable Equalizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| GS1504 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Adaptive Equalizer |
| GS1504_04 | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Adaptive Equalizer |
| GS1504-CKD | 制造商:Rochester Electronics LLC 功能描述: 制造商:Gennum Corporation 功能描述: |
| GS1504-CKDE3 | 制造商:Gennum Corporation 功能描述:High Performance Cable Equalizer 16-Pin SOIC N |
| GS1504-CTD | 制造商:GENNUM 制造商全稱:GENNUM 功能描述:HDTV Adaptive Equalizer |
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