參數(shù)資料
型號: GS1503-CFZ
廠商: Gennum Corporation
元件分類: Codec
英文描述: HD EMBEDDED AUDIO CODEC
中文描述: 高清嵌入式音頻編解碼
文件頁數(shù): 23/83頁
文件大小: 815K
代理商: GS1503-CFZ
15879 - 4
23 of 83
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1.6.3 Audio Clock Phase Locked Loop
Figure 22 shows the configuration for deriving the
6.144MHz audio clock in AES/EBU audio input mode. The
GS1503 will internally synchronize the AES/EBU audio input
to the corresponding ACLK, using the clock extracted from
the AES/EBU bi-phase mark encoding. This configuration is
not required for serial audio input modes.
See the
Reference Design Section 3 for circuit specifics
.
Fig. 22 Block Diagram of GS1503 Audio Clock PLL
1.6.4 Audio Signal Input Detection
The audio input signal detect registers will be set HIGH in
AES/EBU audio mode when the preamble of the audio input
data is detected 3 times consecutively. In serial audio input
mode, the GS1503 will set the audio input signal detect
registers HIGH when a 48kHz word clock is detected at the
corresponding inputs. Audio channels 1 to 4 will be set
when WCINA is validated, and audio channels 5 to 8 when
WCINB is validated. Host Interface register 010h, bits 6-3,
report the individual audio channels pairs detected.
Y/Cb/Cr[19:0]
VIN[19:0]
AIN5/6
GS1503
AIN1/2
AIN3/4
AIN7/8
ACLKA
ACLKB
Audio Channels 1 & 2
Audio Channels 3 & 4
Audio Channels 5 & 6
Audio Channels 7 & 8
6.144MHz (128 fs)
PLLCNTA
PLLCNTB
Low
Pass
Filter
VCXO
24.576MHz
VCXO
24.576MHz
÷4
÷4
6.144MHz (128 fs)
Low
Pass
Filter
Register Settings
NAME
DESCRIPTION
ADDRESS
BIT
SETTING
DEFAULT
AUD7/8_DET
Ch7/8 Audio input signal detection (1:Detection)
010
6
-
0
AUD5/6_DET
Ch5/6 Audio input signal detection (1:Detection)
5
-
0
AUD3/4_DET
Ch3/4 Audio input signal detection (1:Detection)
4
-
0
AUD1/2_DET
Ch1/2 Audio input signal detection (1:Detection)
3
-
0
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