參數(shù)資料
型號(hào)： FDC37N958FRTQFP
廠商： Electronic Theatre Controls, Inc.
英文描述： DIODE ZENER SINGLE 200mW 5.1Vz 5mA-Izt 0.0588 2uA-Ir 2 SOD-323 3K/REEL
中文描述： 筆記本電腦的I / O控制器，具有增強(qiáng)型鍵盤和系統(tǒng)控制
文件頁(yè)數(shù)： 93/316頁(yè)
文件大?。?/td> 999K
代理商： FDC37N958FRTQFP
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SMSC DS – FDC37N958FR
Page 87
Rev. 09/01/99
6. The Modem Control output pins are forced
inactive high.
7. Data that is transmitted is immediately
received.
This feature allows the processor to verify the
transmit and receive data paths of the Serial Port.
In the diagnostic mode, the receiver and the
transmitter interrupts are fully operational. The
MODEM Control Interrupts are also operational
but the interrupts' sources are now the lower four
bits of the MODEM Control Register instead of the
MODEM Control inputs. The interrupts are still
controlled by the Interrupt Enable Register.
BITS 5 - 7
These bits are permanently set to logic zero.
LINE STATUS REGISTER (LSR)
Address Offset = 5H, DLAB = X, READ/WRITE
BIT 0
Data Ready (DR). It is set to a logic "1" whenever
a complete incoming character has been received
and transferred into the Receiver Buffer Register
or the FIFO. Bit 0 is reset to a logic "0" by reading
all of the data in the Receive Buffer Register or
the FIFO.
BIT 1
Overrun Error (OE). Bit 1 indicates that data in
the Receiver Buffer Register was not read before
the next character was transferred into the
register,
thereby
destroying
character. In FIFO mode, an overrunn error will
occur only when the FIFO is full and the next
character has been completely received in the
shift register, the character in the shift register is
overwritten but not transferred to the FIFO. The
OE indicator is set to a logic "1" immediately upon
detection of an overrun condition, and reset
whenever the Line Status Register is read.
the
previous
BIT 2
Parity Error (PE). Bit 2 indicates that the received
data character does not have the correct even or
odd parity, as selected by the even parity select
bit. The PE is set to a logic "1" upon detection of
a parity error and is reset to a logic "0" whenever
the Line Status Register is read. In the FIFO
mode this error is associated with the particular
character in the FIFO it applies to. This error is
indicated when the associated character is at the
top of the FIFO.
BIT 3
Framing Error (FE). Bit 3 indicates that the
received character did not have a valid stop bit.
Bit 3 is set to a logic "1" whenever the stop bit
following the last data bit or parity bit is detected
as a zero bit (Spacing level). The FE is reset to a
logic "0" whenever the Line Status Register is
read. In the FIFO mode this error is associated
with the particular character in the FIFO it applies
to. This error is indicated when the associated
character is at the top of the FIFO. The Serial Port
will try to resynchronize after a framing error. To
do this, it assumes that the framing error was due
to the next start bit, so it samples this 'start' bit
twice and then takes in the 'data'.
BIT 4
Break Interrupt (BI). Bit 4 is set to a logic "1"
whenever the received data input is held in the
Spacing state (logic "0") for longer than a full word
transmission time (that is, the total time of the start
bit + data bits + parity bits + stop bits). The BI is
reset after the CPU reads the contents of the Line
Status Register. In the FIFO mode this error is
associated with the particular character in the
FIFO it applies to. This error is indicated when the
associated character is at the top of the FIFO.
When break occurs only one zero character is
loaded into the FIFO. Restarting after a break is
received, requires the serial data (RXD) to be
logic "1" for at least 1/2 bit time.
Note:
Bits 1
through 4 are the error conditions that produce a
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