參數(shù)資料
型號(hào)： FDC37N958FRTQFP
廠(chǎng)商： Electronic Theatre Controls, Inc.
英文描述： DIODE ZENER SINGLE 200mW 5.1Vz 5mA-Izt 0.0588 2uA-Ir 2 SOD-323 3K/REEL
中文描述： 筆記本電腦的I / O控制器，具有增強(qiáng)型鍵盤(pán)和系統(tǒng)控制
文件頁(yè)數(shù)： 49/316頁(yè)
文件大小： 999K
代理商： FDC37N958FRTQFP
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SMSC DS – FDC37N958FR
Page 43
Rev. 09/01/99
RESET_OUT Pin (Hardware Reset)
The RESET_OUT pin is a global reset and clears
all registers except those programmed by the
Specify command. The DOR reset bit is enabled
and must be cleared by the host to exit the reset
state.
DOR Reset vs. DSR Reset (Software Reset)
These two resets are functionally the same. Both
will reset the FDC core, which affects drive status
information and the FIFO circuits. The DSR reset
clears itself automatically while the DOR reset
requires the host to manually clear it. DOR reset
has precedence over the DSR reset. The DOR
reset is set automatically upon a RESET_OUT pin
reset. The user must manually clear this reset bit
in the DOR to exit the reset state.
FDC MODES OF OPERATION
The FDC has three modes of operation, PC/AT
mode, PS/2 mode and Model 30 mode. These
are determined by the state of IDENT and MFM,
bits[3] and [2] respectively of L0-CRF0.
PC/AT mode
- (IDENT high, MFM a "don't care")
The PC/AT register set is enabled, the DMA
enable bit of the DOR becomes valid (The FDC’s
IRQ and DRQ can be hi-Z), and TC and DENSEL
become active high signals.
PS/2 mode
- (IDENT low, MFM high)
This mode supports the PS/2 models 50/60/80
configuration and register set. The DMA bit of the
DOR becomes a "don't care", (the FDC’s IRQ and
DRQ are always valid), TC and DENSEL become
active low.
Model 30 mode
- (IDENT low, MFM low)
This mode supports PS/2 Model 30 configuration
and register set. The DMA enable bit of the DOR
becomes valid (The FDC’s IRQ and DRQ can be
hi-Z), TC is active high and DENSEL is active low.
DMA TRANSFERS
DMA transfers are enabled with the Specify
command and are initiated by the FDC by
activating its DRQ pin during a data transfer
command. The FIFO is enabled directly by
asserting nDACK and addresses need not be
valid.
Note that if the DMA controller (i.e. 8237A) is
programmed to function in verify mode, a pseudo
read is performed by the FDC based only on
nDACK. This mode is only available when the
FDC has been configured into byte mode (FIFO
disabled) and is programmed to do a read. With
the FIFO enabled, the FDC can perform the
above operation by using the new Verify
command; no DMA operation is needed.
CONTROLLER PHASES
For simplicity, command handling in the FDC can
be divided into three phases: Command,
Execution, and Result. Each phase is described
in the following sections.
Command Phase
After a reset, the FDC enters the command phase
and is ready to accept a command from the host.
For each of the commands, a defined set of
command code bytes and parameter bytes has to
be written to the FDC before the command phase
is complete. (Please refer to Table 24 for the
command set descriptions). These bytes of data
must be transferred in the order prescribed.
Before writing to the FDC, the host must examine
the RQM and DIO bits of the Main Status
Register. RQM and DIO must be equal to "1" and
"0" respectively before command bytes may be
written. RQM is set false by the FDC after each
write cycle until the received byte is processed.
The FDC asserts RQM again to request each
parameter byte of the command unless an illegal
command condition is detected. After the last
parameter byte is received, RQM remains "0" and
the FDC automatically enters the next phase as
defined by the command definition.
The FIFO is disabled during the command phase
to provide for the proper handling of the "Invalid
Command" condition.
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參數(shù)描述
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