參數(shù)資料
型號(hào)： FDC37B787QF
廠商： SMSC Corporation
英文描述： Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
中文描述： 超級(jí)I / O與ACPI支持控制器，實(shí)時(shí)時(shí)鐘和消費(fèi)性紅外
文件頁(yè)數(shù)： 93/249頁(yè)
文件大?。?/td> 932K
代理商： FDC37B787QF
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1.
93
The host selects an EPP register and drives
nIOR active.
The chip drives IOCHRDY inactive (low).
If WAIT is not asserted, the chip must wait
until WAIT is asserted.
The chip tri-states the PData bus and
deasserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus is tri-stated, PDIR is
set and the nWRITE signal is valid.
Peripheral drives PData bus valid.
Peripheral deasserts nWAIT, indicating that
PData is valid and the chip may begin the
termination phase of the cycle.
8. a) The chip latches the data from the PData
bus for the SData bus and deasserts
nDATASTB or nADDRSTRB. This marks
the beginning of the termination phase.
b) The chip drives the valid data onto the
SData bus and asserts (releases)
IOCHRDY allowing the host to complete
the read cycle.
9.
Peripheral tri-states the PData bus and
asserts nWAIT, indicating to the host that the
PData bus is tri-stated.
10. Chip may modify nWRITE, PDIR and
nPDATA in preparation for the next cycle.
EPP 1.7 OPERATION
When the EPP 1.7 mode is selected in the
configuration register, the standard and bi-
directional modes are also available. If no EPP
Read, Write or Address cycle is currently
executing, then the PDx bus is in the standard or
bi-directional mode, and all output signals
(STROBE, AUTOFD, INIT) are as set by the SPP
Control Port and direction is controlled by PCD of
the Control port.
In EPP mode, the system timing is closely coupled
to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The
timer indicates if more than 10usec have elapsed
from the start of the EPP cycle (nIOR or nIOW
asserted) to the end of the cycle nIOR or nIOW
deasserted). If a time-out occurs, the current EPP
2.
3.
4.
5.
6.
7.
cycle is aborted and the time-out condition is
indicated in Status bit 0.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bits D0, D1
and D3 are set to zero. Also, bit D5 (PCD) is a
logic "0" for an EPP write or a logic "1" for and
EPP read.
EPP 1.7 Write
The timing for a write operation (address or data)
is shown in timing diagram EPP 1.7 Write Data or
Address cycle. IOCHRDY is driven active low
when nWAIT is active low during the EPP cycle.
This can be used to extend the cycle time. The
write cycle can complete when nWAIT is inactive
high.
Write Sequence of Operation
1.
The host sets PDIR bit in the control register
to a logic "0". This asserts nWRITE.
2.
The host selects an EPP register, places data
on the SData bus and drives nIOW active.
3.
The chip places address or data on PData
bus.
4.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
5.
If
nWAIT
is
asserted,
deasserted until the peripheral deasserts
nWAIT or a time-out occurs.
6. When the host deasserts nIOW the chip
deasserts nDATASTB or nADDRSTRB and
latches the data from the SData bus for the
PData bus.
7.
Chip may modify nWRITE, PDIR and
nPDATA in preparation of the next cycle.
EPP 1.7 Read
The timing for a read operation (data) is shown in
timing diagram EPP 1.7 Read Data cycle.
IOCHRDY is driven active low when nWAIT is
active low during the EPP cycle. This can be used
to extend the cycle time. The read cycle can
complete when nWAIT is inactive high.
IOCHRDY
is
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