參數(shù)資料
型號(hào)： FDC37B787QF
廠商： SMSC Corporation
英文描述： Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
中文描述： 超級(jí)I / O與ACPI支持控制器，實(shí)時(shí)時(shí)鐘和消費(fèi)性紅外
文件頁(yè)數(shù)： 75/249頁(yè)
文件大?。?/td> 932K
代理商： FDC37B787QF
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LINE CONTROL REGISTER (LCR)
Address Offset = 3H, DLAB = 0, READ/WRITE
This register contains the format information of the
serial line. The bit definitions are:
Bits 0 and 1
These two bits specify the number of bits in each
transmitted or received serial character. The
encoding of bits 0 and 1 is as follows:
The Start, Stop and Parity bits are not included in
the word length.
76
BIT 1
0
0
1
1
BIT 0
0
1
0
1
WORD LENGTH
5 Bits
6 Bits
7 Bits
8 Bits
Bit 2
This bit specifies the number of stop bits in each
transmitted or received serial character. The
following table summarizes the information. Note:
The receiver will ignore all stop bits beyond the
first, regardless of the number used in transmitting.
Bit 3
Parity Enable bit. When bit 3 is a logic "1", a parity
bit is generated (transmit data) or checked
(receive data) between the last data word bit and
the first stop bit of the serial data. (The parity bit is
used to generate an even or odd number of 1s
when the data word bits and the parity bit are
summed).
Bit 4
Even Parity Select bit. When bit 3 is a logic "1"
and bit 4 is a logic "0", an odd number of logic "1"'s
is transmitted or checked in the data word bits and
the parity bit. When bit 3 is a logic "1" and bit 4 is
a logic "1" an even number of bits is transmitted
and checked.
Bit 5
Stick Parity bit. When bit 3 is a logic "1" and bit 5
is a logic "1", the parity bit is transmitted and then
detected by the receiver in the opposite state
indicated by bit 4.
Bit 6
Set Break Control bit. When bit 6 is a logic "1", the
transmit data output (TXD) is forced to the
Spacing or logic "0" state and remains there (until
reset by a low level bit 6) regardless of other
transmitter activity. This feature enables the Serial
Port to alert a terminal in a communications
system.
Bit 7
Divisor Latch Access bit (DLAB). It must be set
high (logic "1") to access the Divisor Latches of the
Baud Rate Generator during read or write
operations. It must be set low (logic "0") to access
the Receiver Buffer Register, the Transmitter
Holding Register, or the Interrupt Enable Register.
MODEM CONTROL REGISTER (MCR)
Address Offset = 4H, DLAB = X, READ/WRITE
This 8 bit register controls the interface with the
MODEM or data set (or device emulating a
MODEM). The contents of the MODEM control
register are described below.
Bit 0
This bit controls the Data Terminal Ready (nDTR)
output. When bit 0 is set to a logic "1", the nDTR
output is forced to a logic "0". When bit 0 is a logic
"0", the nDTR output is forced to a logic "1".
BIT 2
0
1
1
1
1
WORD LENGTH
--
5 bits
6 bits
7 bits
8 bits
NUMBER OF
STOP BITS
1
1.5
2
2
2
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