參數(shù)資料
型號： FDC37B787QF
廠商： SMSC Corporation
英文描述： Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
中文描述： 超級I / O與ACPI支持控制器，實時時鐘和消費性紅外
文件頁數(shù)： 92/249頁
文件大?。?/td> 932K
代理商： FDC37B787QF
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In EPP mode, the system timing is closely coupled
to the EPP timing. For this reason, a watchdog
timer is required to prevent system lockup. The
timer indicates if more than 10usec have elapsed
from the start of the EPP cycle (nIOR or nIOW
asserted) to nWAIT being deasserted (after
command). If a time-out occurs, the current EPP
cycle is aborted and the time-out condition is
indicated in Status bit 0.
During an EPP cycle, if STROBE is active, it
overrides the EPP write signal forcing the PDx bus
to always be in a write mode and the nWRITE
signal to always be asserted.
Software Constraints
Before an EPP cycle is executed, the software
must ensure that the control register bit PCD is a
logic "0" (ie a 04H or 05H should be written to the
Control port). If the user leaves PCD as a logic
"1", and attempts to perform an EPP write, the
chip is unable to perform the write (because PCD
is a logic "1") and will appear to perform an EPP
read on the parallel bus, no error is indicated.
EPP 1.9 Write
The timing for a write operation (address or data)
is shown in timing diagram EPP Write Data or
Address cycle. IOCHRDY is driven active low at
the start of each EPP write and is released when
it has been determined that the write cycle can
complete. The write cycle can complete under
the following circumstances:
1.
If the EPP bus is not ready (nWAIT is active
low) when nDATASTB or nADDRSTB goes
active then the write can complete when
nWAIT goes inactive high.
2.
If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go active
low before changing the state of nDATASTB,
nWRITE or nADDRSTB. The write can
complete once nWAIT is determined inactive.
Write Sequence of operation
92
1.
The host selects an EPP register, places data
on the SData bus and drives nIOW active.
The chip drives IOCHRDY inactive (low).
If WAIT is not asserted, the chip must wait
until WAIT is asserted.
The chip places address or data on PData
bus, clears PDIR, and asserts nWRITE.
Chip asserts nDATASTB or nADDRSTRB
indicating that PData bus contains valid
information, and the WRITE signal is valid.
Peripheral deasserts nWAIT, indicating that
any setup requirements have been satisfied
and the chip may begin the termination phase
of the cycle.
a) The chip deasserts nDATASTB or
nADDRSTRB, this marks the beginning
of the termination phase. If it has not
already done so, the peripheral should
latch the information byte now.
b) The chip latches the data from the SData
bus for the PData bus and asserts
(releases) IOCHRDY allowing the host to
complete the write cycle.
Peripheral asserts nWAIT, indicating to the
host that any hold time requirements have
been
satisfied
and
termination of the cycle.
Chip may modify nWRITE and nPDATA in
preparation for the next cycle.
EPP 1.9 Read
The timing for a read operation (data) is shown in
timing diagram EPP Read Data cycle. IOCHRDY
is driven active low at the start of each EPP read
and is released when it has been determined that
the read cycle can complete. The read cycle can
complete under the following circumstances:
1
If the EPP bus is not ready (nWAIT is active
low) when nDATASTB goes active then the
read can complete when nWAIT goes inactive
high.
2.
If the EPP bus is ready (nWAIT is inactive
high) then the chip must wait for it to go active
low before changing the state of WRITE or
before nDATASTB goes active. The read can
complete once nWAIT is determined inactive.
Read Sequence of Operation
2.
3.
4.
5.
6.
7.
8.
acknowledging
the
9.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
FDC37B787QFP 功能描述:輸入/輸出控制器接口集成電路 Enhanced Super I/O Controller RoHS:否 制造商:Silicon Labs 產(chǎn)品: 輸入/輸出端數(shù)量: 工作電源電壓: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-64 封裝:Tray
FDC37B78X 制造商:SMSC 制造商全稱:SMSC 功能描述:Enhanced Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
FDC37B78X_07 制造商:SMSC 制造商全稱:SMSC 功能描述:Super I/O Controller with ACPI Support, Real Time Clock and Consumer IR
FDC37B802 制造商:Rochester Electronics LLC 功能描述:
FDC37B802QFP 制造商:Rochester Electronics LLC 功能描述:- Bulk
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