參數(shù)資料
型號: DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù): 87/135頁
文件大?。?/td> 585K
代理商: DS3112N
DS3112
87 of 135
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Note:
Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 31/BERT 32-Bit Bit Counter (BBC0 to BBC31).
This 32-bit counter will increment for each
data bit (i.e., clock received). This counter is not disabled when the receive BERT loses synchronization.
This counter can be cleared by toggling the LC control bit in BERTC0. This counter saturates and will
not rollover. Upon saturation, the BBCO status bit in the BERTEC0 register will be set. This error
counter starts counting when the BERT goes into receive synchronization (RLOS = 0 or SYNC = 1) and
it will not stop counting when the BERT loses synchronization. It is recommended that the host toggle the
LC bit in BERTC0 register once the BERT has synchronized and then toggle the LC bit again when the
error checking period is complete. If the device loses synchronization during this period, then the
counting results are suspect.
BERTBC0
BERT 32-Bit Bit Counter (lower word)
78h
7
6
5
4
3
2
1
0
BBC7
0
BBC6
0
BBC5
0
BBC4
0
BBC3
0
BBC2
0
BBC1
0
BBC0
0
15
14
13
12
11
10
9
8
BBC15
0
BBC14
0
BBC13
0
BBC12
0
BBC11
0
BBC10
0
BBC9
0
BBC8
0
BERTBC1
BERT 32-Bit Bit Counter (upper word)
7Ah
7
6
5
4
3
2
1
0
BBC23
0
BBC22
0
BBC21
0
BBC20
0
BBC19
0
BBC18
0
BBC17
0
BBC16
0
15
14
13
12
11
10
9
8
BBC31
0
BBC30
0
BBC29
0
BBC28
0
BBC27
0
BBC26
0
BBC25
0
BBC24
0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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