參數(shù)資料
型號： DS3112N
英文描述： RECT BRIDGE GPP 15A 600V GBJ
中文描述： 坦佩化T3/E3復用器3.3化T3/E3成幀器和M13/E13/G.747復用器
文件頁數(shù)： 84/135頁
文件大?。?/td> 585K
代理商： DS3112N
DS3112
84 of 135
Bit 5/Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 6/Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Bit 7/Pattern Bank Select (PBS)
0 = PS[2:0] select a pattern from Pattern Bank 0
1 = PS[2:0] select a pattern from Pattern Bank 1
Bits 8 to 11/Repetitive Pattern Length Bits 5 (RPL0 to RPL3).
RPL0 is the LSB and RPL3 is the MSB of a nibble that
describes the how long the repetitive pattern is.
The
valid range is 17 (0000) to 32 (1111). These bits are
ignored if the receive BERT is programmed for
a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the
length to an integer number of the desired length that is less than or equal to 32. For example, to create a
6-bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).
Repetitive Pattern Length Map
Length
Code
Length Code
17 Bits
0000
18 Bits
0001
21 Bits
0100
22 Bits
0101
25 Bits
1000
26 Bits
1001
29 Bits
1100
30 Bits
1101
Bit 13/Interrupt Enable for Counter Overflow (IEOF).
Allows the receive BERT to cause an interrupt
if either the Bit Counter or the Error Counter overflows (Figure 8.2A).
0 = interrupt masked
1 = interrupt enabled
Bit 14/Interrupt Enable for Bit Error Detected (IEBED).
Allows the receive BERT to cause an
interrupt if a bit error is detected (Figure 8.2A).
0 = interrupt masked
1 = interrupt enabled
Bit 15/Interrupt Enable for Change of Synchronization Status (IESYNC).
Allows the receive BERT
to cause an interrupt if there is a change of state in the synchronization status (i.e., the receive BERT
either goes into or out of synchronization) (Figure 8.2A).
0 = interrupt masked
1 = interrupt enabled
Length
19 Bits
23 Bits
27 Bits
31 Bits
Code
0010
0110
1010
1101
Length Code
20 Bits
24 Bits
28 Bits
32 Bits
0011
0111
1011
1111
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相關代理商/技術參數(shù)
參數(shù)描述
DS3112N+ 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+W 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112NC1 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube
DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS3112RD 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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