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參數(shù)資料
| 型號： | DS3112N |
| 英文描述： | RECT BRIDGE GPP 15A 600V GBJ |
| 中文描述： | 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器 |
| 文件頁數(shù)： | 40/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112N |
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DS3112
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Bit 9/Change in T3/E3 Framer Status (T3E3SR).
This read-only real-time status bit will be set to a one
when the T3/E3 framer has detected a change in RAI, AIS, LOF, LOS, or T3 Idle signal or has detected
the start of a Transmit or Receive Frame and the associated interrupt enable bit is set in the T3E3SR
register. See the T3E3SR register description in Section 5.3 for more details. This bit will be cleared
when the T3E3SR register is read. The setting of this status bit can cause a hardware interrupt to occur if
the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when the T3E3SR register is read (Figure 4.3I).
Bit 10/Loss Of Transmit Clock Detected (LOTC).
This read-only real-time status bit will be set to a
one when the device detects that the FTCLK clock has not toggled for 200ns (±100ns). This bit will be
cleared when a clock is detected at the FTCLK input. The setting of this status bit can cause a hardware
interrupt to occur if the LOTC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the device detects a clock at FTCLK. The HRCLK checks for the
presence of the FTCLK. On reset, both the LOTC and LORC status bits will be set and then immediately
cleared if the clock is present.
Bit 11/Loss Of Receive Clock Detected (LORC).
This read-only real-time status bit will be set to a one
when the device detects that the HRCLK clock has not toggled for 200ns (±100ns). This bit will be
cleared when a clock is detected at the HRCLK input. The setting of this status bit can cause a hardware
interrupt to occur if the LORC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the device detects a clock at HRCLK. The FTCLK checks for the
presence of the HRCLK. On reset, both the LOTC and LORC status bits will be set and then immediately
cleared if the clock is present.
Bit 12/State of the T3E3MS Input Signal (T3E3MS).
This read-only real-time status bit reflects the
current state of the external T3E3MS input signal. This status bit cannot generate an interrupt.
Bit 13/State of the G.747E Input Signal (G.747E).
This read-only real-time status bit reflects the
current state of the external G.747E input signal. This status bit cannot generate an interrupt.
BERT STATUS BIT FLOW
Figure 4.3D
Note:
All event and alarm latches above are cleared when the BERTEC0 register is read.
Alarm Latch
Change in State Detect
RLOS
(BERTEC0
Bit 4)
Internal RLOS
Signal from
BERT
Event Latch
Internal Bit
Error Detected
Signal from
BERT
Event Latch
Internal Counter
Overflow
Signal from
BERT
OR
BED
(BERTEC0
Bit 3)
BECO or BBCO
(BERTEC0
Bits 1 & 2)
Mask
BERT
(IMSR Bit 2)
INT*
Hardware
Signal
BERT
Status Bit
(MSR Bit 2)
Mask
IESYNC (BERTC0 Bit 15)
Mask
Mask
IEBED (BERTC0 Bit 14)
IEOF (BERTC0 Bit 13)
Event Latch
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PDF描述 |
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| DS3112RD | RECT BRIDGE GPP 15A 800V GBJ |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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