參數(shù)資料
型號： DS3112N
英文描述： RECT BRIDGE GPP 15A 600V GBJ
中文描述： 坦佩化T3/E3復用器3.3化T3/E3成幀器和M13/E13/G.747復用器
文件頁數(shù)： 27/135頁
文件大?。?/td> 585K
代理商： DS3112N
DS3112
27 of 135
2.9 JTAG Signal Description
Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this signal should be pulled high.
Signal Name:
JTDI
Signal Description:
JTAG IEEE 1149.1 Test Serial Data Input
Signal Type:
Input (with internal 10k pullup)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal
should be pulled high. This signal has an internal pullup.
Signal Name:
JTDO
Signal Description:
JTAG IEEE 1149.1 Test Serial Data Output
Signal Type:
Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal
should be left open circuited.
Signal Name:
JTRST*
Signal Description:
JTAG IEEE 1149.1 Test Reset
Signal Type:
Input (with internal 10k pullup)
This signal is used to asynchronously reset the test access port controller. At power-up, JTRST must be
set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this signal should be held low. This signal has an
internal pullup.
Signal Name:
JTMS
Signal Description:
JTAG IEEE 1149.1 Test Mode Select
Signal Type:
Input (with internal 10k pullup)
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various
defined IEEE 1149.1 states. If not used, this signal should be pulled high. This signal has an internal
pullup.
2.10 Supply, Test, Reset, and Mode Signal Description
Signal Name:
RST*
Signal Description:
Global Hardware Reset
Signal Type:
Input (with internal 10k pullup)
This active low asynchronous signal causes the device to be reset. When this signal is forced low, it
causes all of the internal registers to be forced to 00h and the high speed T3/E3 ports as well as the low
speed T1/E1 ports to source an unframed all ones data pattern. The device will be held in a reset state as
long as this signal is low. This signal should be activated after the hardware configuration signals (LIEN
and T3E3MS) and the clocks (FTCLK, LTCLK, HRCLK, and LITCLK) are stable and must be returned
high before the device can be configured for operation.
JTCLK
JTAG IEEE 1149.1 Test Serial Clock
Input
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相關代理商/技術參數(shù)
參數(shù)描述
DS3112N+ 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+W 功能描述:網(wǎng)絡控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112NC1 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube
DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS3112RD 功能描述:網(wǎng)絡控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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