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參數(shù)資料
| 型號： | DS3112N |
| 英文描述： | RECT BRIDGE GPP 15A 600V GBJ |
| 中文描述： | 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器 |
| 文件頁數(shù)： | 54/135頁 |
| 文件大?。?/td> | 585K |
| 代理商： | DS3112N |
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DS3112
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Bit 3/Remote Alarm Indication Detected (RAI).
This latched read-only alarm status bit will be set to a
one when the T3 or E3 framer detects an incoming Remote Alarm Indication (RAI) signal. This bit will
be cleared when read unless an RAI signal is still present. A change in state of the RAI detection can
cause a hardware interrupt to occur if the RAI bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is
set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read. The RAI alarm detection criteria is described in
Tables 5.3A and 5.3B. RAI can also be indicated via the FEAC codes when the device is operated in the
C-Bit Parity Mode.
Bit 4/T3 Idle Signal Detected (T3IDLE).
This latched read-only alarm status bit will be set to a one
when the T3 framer detects an incoming idle signal. This bit will be cleared when read unless the idle
signal is still present. A change in state of idle detection can cause a hardware interrupt to occur if the
IDLE bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The IDLE detection criteria is described in Table
5.3A. The interrupt will be allowed to clear when this bit is read. When the DS3112 is operated in the E3
mode, this status bit should be ignored.
Bit 5/Transmit T3/E3 Start Of Frame (TSOF).
This latched read-only event-status bit will be set to a
one on each T3/E3 transmit frame boundary. This bit is a software version of the FTSOF hardware signal
and it will be cleared when read. The setting of this bit can cause a hardware interrupt to occur if the
TSOF bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one.
Bit 6/Receive T3/E3 Start Of Frame (RSOF).
This latched read-only event status bit will be set to a one
on each T3/E3 receive frame boundary. This bit is a software version of the FRSOF hardware signal and
it will be cleared when read. The setting of this bit can cause a hardware interrupt to occur if the RSOF
bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one.
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PDF描述 |
|---|---|
| DS3112RD | RECT BRIDGE GPP 15A 800V GBJ |
| DS3134 | Chateau Channelized T1 And E1 And HDLC Controller |
| DS3160 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| DS3171 | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
| DS3171N | Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DS3112N+ | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112N+W | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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