參數(shù)資料
型號： DS3112N
英文描述： RECT BRIDGE GPP 15A 600V GBJ
中文描述： 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù)： 39/135頁
文件大?。?/td> 585K
代理商： DS3112N
DS3112
39 of 135
Bit 2/Change in BERT Status (BERT).
This read-only real-time status bit will be set to a one if there is
a major change of status in the BERT receiver and the associated interrupt enable bit is set in the
BERTCO register. A major change of status is defined as either a change in the receive synchronization
(i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an
overflow has occurred in either the Bit Counter or the Error Counter. The host must read the status bits of
the BERT in the BERT Status Register (BERTEC0) to determine the change of state. This bit will be
cleared when the BERTEC0 is read and will not be set again until the BERT has experienced another
change of state. The setting of this status bit can cause a hardware interrupt to occur if the BERT bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when
the BERTEC0 register is read (Figure 4.3D).
Bit 3/Change in HDLC Status (HDLC).
This read-only real-time status bit will be set to a one if there is
a change of status in the HDLC controller and the associated interrupt enable bit is set in the IHSR
register. The host must read the status bits of the HDLC in the HDLC Status Register (HSR) to determine
the change of state. This bit will be cleared when the HSR is read and will not be set again until the
HDLC has experienced another change of state. The setting of this status bit can cause a hardware
interrupt to occur if the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the HSR register is read (Figure 4.3E).
Bit 4/Change in FEAC Status (FEAC).
This read-only real-time status bit will be set to a one when the
FEAC controller has detected and verified a new Far End Alarm and Control (FEAC) 16-bit code word.
This bit will be cleared when the FEAC Status Register (FSR) is read and will not be set again until the
FEAC controller has detected and verified another new code word. The setting of this status bit can cause
a hardware interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when the FSR register is read.
Bit 5/Change in T2/E2 LOF or AIS Status (T2E2SR1).
This read-only real-time status bit will be set to
a one when one or more of the T2/E2/G.747 framers have detected a change in either Loss Of Frame
(LOF) or Alarm Indication Signal (AIS) and the associated interrupt enable bit is set in the T2E2SR1
register. See the T2E2SR1 register description in Section 6.3 for more details. This bit will be cleared
when the T2E2SR1 register is read. The setting of this status bit can cause a hardware interrupt to occur if
the T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when the T2E2SR1 register is read (Figure 4.3F).
Bit 6/Change in T2/E2 RAI Status (T2E2SR2).
This read-only real-time status bit will be set to a one
when one or more of the T2/E2/G.747 framers have detected a change in the detection of the Remote
Alarm Indication (RAI) signal and the interrupt enable (bit 7) is set in the T2E2SR2 register. See the
T2E2SR2 register description in Section 6.3 for more details. This bit will be cleared when the T2E2SR2
register is read. The setting of this status bit can cause a hardware interrupt to occur if the T2E2SR2 bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when
the T2E2SR2 register is read (Figure 4.3G).
Bit 8/T1 Loopback Detected (T1LB).
This read-only real-time status bit will be set to a one when one or
more of the T2 framers have detects an active T1 loopback command. See the T1LBSR1 and T1LBSR2
register descriptions in Section 7.3 for more details. This bit will be cleared when the T1 loopback
command is no longer active on any of the lines. The setting of this status bit can cause a hardware
interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the none of the T2 framers detects an active T1 loopback
command (Figure 4.3H).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS3112N+ 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112N+W 功能描述:網(wǎng)絡(luò)控制器與處理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
DS3112NC1 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube
DS3112ND1E 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述:
DS3112RD 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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