參數(shù)資料
型號(hào): DS3112N
英文描述: RECT BRIDGE GPP 15A 600V GBJ
中文描述: 坦佩化T3/E3復(fù)用器3.3化T3/E3成幀器和M13/E13/G.747復(fù)用器
文件頁數(shù): 79/135頁
文件大?。?/td> 585K
代理商: DS3112N
DS3112
79 of 135
Bits 0 to 11/T1 Line Loopback Command Status for Ports 17 to 28 (LLB17 to LLB28).
These read-
only real-time status bits will be set to a one when the corresponding T2 framer detects that the C3 bit is
the inverse of the C1 and C2 bits for 5 consecutive frames. These bits will be allowed to clear when the
C3 bit is not the inverse of the C1 and C2 bits for five consecutive frames. LLB17 corresponds to T1/E1
Port 17, LLB18 corresponds to T1/E1 Port 18, and so on. The setting of any of the bits in T1LBSR1 or
T1LBSR2 can cause a hardware interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR)
is set to a one. In the E3 and G.747 Modes, these bits are meaningless and should be ignored.
T1LBSR1 and T1LBSR2 STATUS BIT FLOW
Figure 7.3A
LLB1
(T1LBSR1
Bit 0)
Loopback Command
Signal from
T2/E2 Framer
7.4 T1/E1 DROP AND INSERT CONTROL REGISTER DESCRIPTION
Register Name:
T1E1SDP
Register Description:
T1/E1 Select Register for Receive Drop Ports A and B
Register Address:
60h
Bit #
7
6
5
Name
n/a
n/a
n/a
Default
-
-
-
Bit #
15
14
13
Name
n/a
n/a
n/a
Default
-
-
-
Note:
Bits that are underlined are read-only; all other bits are read-write.
4
3
2
1
0
DPAS4
0
DPAS3
0
DPAS2
0
DPAS1
0
DPAS0
0
12
11
10
9
8
DPBS4
0
DPBS3
0
DPBS2
0
DPBS1
0
DPBS0
0
Internal T1
OR
Mask
T1LB
(IMSR Bit 8)
INT*
Hardware
Signal
T1LB
Status Bit
(MSR Bit 8)
LLB2
(T1LBSR1
Bit 1)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
LLB28
(T1LBSR2
Bit 11)
Internal T1
Loopback Command
Signal from
T2/E2 Framer
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