參數(shù)資料
型號: CYP15G0403DXB
英文描述: Physical Layer Devices
中文描述: 物理層設(shè)備
文件頁數(shù): 47/78頁
文件大?。?/td> 1555K
代理商: CYP15G0403DXB
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 47 of 78
Input & Output Standard Timing Delay Adjustments
All the timing specifications in this data sheet are specified based on 3.3V PCI compliant inputs and outputs (fast slew rates
[34]
).
Apply following adjustments if the inputs and outputs are configured to operate at other standards.
Input/Output
Standard
LVTTL
LVCMOS
LVCMOS3
LVCMOS2
LVCMOS18
3.3V PCI
GTL+
SSTL3 I
SSTL3 II
SSTL2 I
SSTL2 II
HSTL I
HSTL II
HSTL III
HSTL IV
Output Delay Adjustments
t
EA
0
0
0.05
0.1
0.7
0
0.6
[35]
0.6
[35]
0.3
0.4
0.1
0.2
0.6
0.4
0.6
0.7
Input Delay Adjustments
t
CKIN
0
0
0.1
0.2
0.4
0
0.4
0.3
0.3
0.5
0.5
0.5
0.5
0.5
0.5
t
IOD
0.2
0.2
0.3
0.5
2.1
0
t
ER
0
0
0
0
0.1
0
0.9
[35]
0.1
0
0
0
0.5
0.5
0.1
0
t
IOIN
0
0
0.1
0.2
0.5
0
0.5
0.5
0.5
0.9
0.9
0.5
0.5
0.5
0.5
t
IOREGPIN
0
0
0.2
0.4
0.3
0
0.2
0.3
0.3
0.6
0.6
0.3
0.3
0.3
0.3
0.3
0.2
0.4
0.2
0.9
0.8
0.5
0.6
Notes:
34. For
slow slew rate
output delay adjustments, refer to
Warp
software
s static timing analyzer results.
35. These delays are based on falling edge output. The rising edge delay depends on the size of pull up resistor and termination voltage.
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