參數(shù)資料
型號： CYP15G0403DXB
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁數(shù)： 34/78頁
文件大小： 1555K
代理商： CYP15G0403DXB
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 34 of 78
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature .................................
–
65
°
C to +150
°
C
Soldering Temperature...................................................220
°
C
Ambient Temperature with
Power Applied...............................................
–
40
°
C to +85
°
C
Junction Temperature....................................................135
°
C
V
CC
relative to Ground Potential......................
–
0.5V to 4.2V
V
CCIO
relative to Ground Potential...................
–
0.5V to 4.6V
DC Voltage Applied to Outputs in High Z State
–
0.5V to 4.5V
Output Current into LVCMOS Outputs (LOW).............30 mA
DC Input voltage...............................................
–
0.5V to 4.5V
DC Current into Outputs...................... ...................± 20 mA
[6]
Static Discharge Voltage
...............................................>
2001 V
(per MIL-STD-883, Method 3015)
Latch-Up Current
...........................................................>
200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
V
CC
V
DDQ
3.3V
±
10%
1.4V to 1.6V
Operating Range
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
Junction
Temperature
0
°
C to +85
°
C
Output
Condition
3.3V
2.5V
1.8V
1.5V
V
CCIO
3.3V ± 0.3V
2.5V ± 0.2V
1.8V ± 0.15V
1.5V ± 0.1V
V
CC
3.3V
±
0.3V
V
CCJTAG
/
V
CCCNFG
Same as
V
CCIO
V
CCPLL
Same as
V
CC
V
CCPRG
3.3V
±
0.3V
Notes:
6.
DC current into outputs is 36 mA with HSTL III and 48 mA with HSTL IV
AC Test Loads and Waveforms
Notes:
7.
8.
Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only.
The LVTTL switching threshold is 1.4V. All timing references are made relative to the point where the respective rising or falling signal edge crosses this
threshold voltage.
2.0V
0.8V
3.0V
V
th
=1.4V
GND
2.0V
0.8V
(a) LVTTL AC Test Load
(b) CML AC Test Load
< 1 ns
< 1 ns
80%
20%
80%
20%
(c) LVTTL Input Test Waveform
(d) PECL Input Test Waveform
C
L
R
L
R
L
=100
C
L
< 5 pF
(Includes fixture and
probe capacitance)
V
IHE
3.0V
V
IHE
V
ILE
V
ILE
[7]
[7]
≤
250 ps
≤
250 ps
[8]
V
th
=1.4V
3.3V
OUTPUT
R1
R2
C
L
R1=365
R2=267
C
L
≤
7 pF
(Includes fixture and
probe capacitance)
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