參數(shù)資料
型號: CYP15G0403DXB
英文描述: Physical Layer Devices
中文描述: 物理層設(shè)備
文件頁數(shù): 43/78頁
文件大?。?/td> 1555K
代理商: CYP15G0403DXB
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 43 of 78
Receive Serial Inputs and CDR PLL Characteristics
Parameter
Description
Min.
Max.
Unit
t
RXLOCK
Receive PLL lock to input data stream (cold start)
10
ms
Receive PLL lock to input data stream
2500
UI
t
RXUNLOCK
t
SA
t
EFW
Receive PLL Unlock Rate
Static Alignment
[19, 26]
Error Free Window
[19, 27, 28]
TBD
TBD
ns
ps
0.5
UI
Notes:
26. Static alignment is a measure of the alignment of the Receiver sampling point to the center of a bit. Static alignment is measured by sliding one bit edge in
3,000 nominal transitions until a character error occurs.
27. Receiver UI (Unit Interval) is calculated as 1/(f
*20) (when RXRATE = HIGH) or 1/(f
* 10) (when RXRATE = LOW) if no data is being received, or 1/(f
* 20)
(when RXRATE = HIGH) or 1/(f
* 10) (when RXRATE = LOW) of the remote transmitter if data is being received. In an operating link this is equivalent to t
.
28. Error Free Window is a measure of the time window between bit centers where a transition may occur without causing a bit sampling error. EFW is measured
over the operating range, input jitter
<
50% Dj.
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