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參數(shù)資料
| 型號： | CYP15G0403DXB |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設備 |
| 文件頁數(shù)： | 10/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0403DXB |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 10 of 78
The clocks for each port of the Dual-Port configuration are
selected from four global clocks and two local clocks. One local
clock is sourced from the horizontal channel and the other from
the vertical channel. The data outputs of the dual-port memory
can also be registered. Clocks for the output registers are also
selected from four global clocks and two local clocks. One
clock polarity mux per port allows the use of true or comple-
ment polarity for input and output clocking purposes.
Arbitration
The Dual-Port configuration of the Channel Memory Block pro-
vides arbitration when both ports access the same address at
the same time. Depending on the memory operation being
attempted, one port always gets priority. See
Table 2
for details
on which port gets priority for read and write operations. An
active-LOW
‘
Address Match
’
signal is generated when an ad-
dress collision occurs.
FIFO (Channel Memory) Configuration
The channel memory blocks are also configurable as synchro-
nous FIFO RAM. In the FIFO mode of operation, the channel
memory block supports all normal FIFO operations without the
use of any general-purpose logic resources in the device.
The FIFO block contains all of the necessary FIFO flag logic,
including the read and write address pointers. The FIFO flags
include an empty/full flag (EF), half-full flag (HF), and program-
mable almost-empty/full (PAEF) flag output. The FIFO config-
uration has the ability to perform simultaneous read and write
operations using two separate clocks. These clocks may be
tied together for a single operation or may run independently
for asynchronous read/write (w.r.t. each other) applications.
The data and control inputs to the FIFO block are driven from
the horizontal or vertical routing channels. The data and flag
outputs are driven onto dedicated routing tracks in both the
horizontal and vertical routing channels. This allows the FIFO
blocks to be expanded by using multiple FIFO blocks on the
same horizontal or vertical routing channel without any speed
penalty.
In FIFO mode, the write and read ports are controlled by sep-
arate clock and enable signals. The clocks for each port are
selected from four global clocks and two local clocks.
One local clock is sourced from the horizontal channel and the
other from the vertical channel. The data outputs from the read
port of the FIFO can also be registered. One clock polarity mux
per port allows using true or complement polarity for read and
write operations. The write operation is controlled by the clock
and the write enable pin. The read operation is controlled by
the clock and the read enable pin. The enable pins can be
sourced from horizontal or vertical channels.
Channel Memory Initialization
The channel memory powers up in an undefined state, but is
set to a user-defined known state during configuration. To fa-
cilitate the use of look-up-table (LUT) logic and ROM applica-
tions, the channel memory blocks can be initialized with a giv-
en set of data when the device is configured at power up. For
LUT and ROM applications, the user cannot write to memory
blocks.
Channel Memory Routing Interface
Similar to LBC outputs, the channel memory blocks feature
dedicated tracks in the horizontal and vertical routing channels
for the data outputs and the flag outputs, as shown in
Figure
7
. This allows the channel memory blocks to be expanded
easily. These dedicated lines can be routed to I/O pins as chip
outputs or to other logic block clusters to be used in logic equa-
tions.
Figure 7. Block Diagram of Channel Memory Block
I/O Banks
The PSI interfaces the horizontal and vertical routing channels
to the pins through I/O banks. There are several I/O banks per
device as shown in
Figure 8
and all I/Os from an I/O bank are
located in the same section of a package for PCB layout con-
venience. There are two kinds of I/O banks; fixed-signal I/O
banks and user-programmable I/O banks.
The first fixed-signal bank is the Serial Signal Bank. This bank
includes all differential serial data transmission and receive
signals. The second bank is the Transceiver Control Bank.
This bank includes all static signal pins required for the config-
uration and operation of the transceiver blocks in each of the
PSI devices.
Table 2. Arbitration Result: Address Match Signal
Becomes Active
Port A
Read
Port B
Read
Result of
Arbitration
No arbitration
required
Port A gets
priority
Comment
Both ports read at the
same time
If Port B requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port A
If Port A requests first
then it will read the cur-
rent data. The output will
then change to the newly
written data by Port B
Port B is blocked until
Port A is finished writing
Write
Read
Read
Write
Port B gets
priority
Write
Write
Port A gets
priority
4096-bit Dual-Port
Array
Configurable as
Async/Sync Dual-Port or
Sync FIFO
Configurable as
4Kx1, 2Kx2, 1Kx4 and
512x8 block sizes
Horizontal Channel
All channel memory
inputs are driven from
the routing channels
All channel memory outputs
drive dedicated tracks in the
routing channels
GCLK[3:0]
Global Clock
Signals
V
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