- 您現(xiàn)在的位置：買賣IC網 > PDF目錄367000 > CYP15G0403DXB Physical Layer Devices PDF資料下載
參數(shù)資料
| 型號： | CYP15G0403DXB |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設備 |
| 文件頁數(shù)： | 12/78頁 |
| 文件大小： | 1555K |
| 代理商： | CYP15G0403DXB |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 12 of 78
.
I/O Cell
Figure 9
is a block diagram of the PSI I/O cell. The I/O cell
contains a three-state input buffer, an output buffer, and a reg-
ister that can be configured as an input or output register. The
output buffer has a slew rate control option that can be used to
configure the output for a slower slew rate. The input of the
device and the pin output can each be configured as registered
or combinatorial, however only one path can be configured as
registered in a given design.
The output enable can be selected from one of the four global
control signals or from one of two Output Control Channel
(OCC) signals. The output enable can be configured as always
enabled or always disabled, or it can be controlled by one of
the remaining inputs to the mux. The selection is done via a
mux that includes V
CC
and GND as inputs.
One of the global clocks can be selected as the clock for the
I/O cell register. The clock mux output is an input to a clock
polarity mux that allows the input/output register to be clocked
on either edge of the clock.
Slew Rate Control
The output buffer has a slew rate control option. This allows
the ouput buffer to slew at a fast rate (3 V/ns) or a slow rate (1
V/ns). All I/Os default to fast slew rate. For designs concerned
with meeting FCC emissions standards the slow edge pro-
vides for lower system noise. For designs requiring very high
performance the fast edge rate provides maximum system
performance.
Programmable Bus Hold
On each I/O pin, user-programmable bus-hold is included.
Bus-hold, which is an improved version of the popular internal
pull-up resistor, is a weak latch connected to the pin that does
not degrade the device
’
s performance. As a latch, bus-hold
maintains the last state of a pin when the pin is placed in a
high-impedance state, thus reducing system noise in bus-in-
terface applications. Bus-hold additionally allows unused de-
vice pins to remain unconnected on the board, which is partic-
ularly useful during prototyping as designers can route new
signals to the device without cutting trace connections to V
CC
or GND. For more information, see the application note
“
Un-
derstanding Bus-Hold
A Feature of Cypress CPLDs.
”
Clocks
PSI - Frequency Agile devices have four dedicated clock input
pins (GCLK[3:0]) to accept system clocks. One of these clocks
(GCLK[0]) may be selected to drive an on-chip Phase-Locked
Loop (PLL) for frequency modulation (see
Figure 10
for de-
tails). The global clock tree for a PSI - Frequency Agile devices
can be driven by a combination of the dedicated clock pins
and/or the PLL-derived clocks. The global clock tree consists
of four global clocks that go to every macrocell, memory block,
and I/O cell.
Clock Tree Distribution
The global clock tree performs two primary functions. First, the
clock tree generates the four global clocks by multiplexing four
dedicated clocks from the package pins and four PLL driven
clocks. Second, the clock tree distributes the four global clocks
to every cluster, channel memory, and I/O block on the die. The
global clock tree is designed such that the clock skew is mini-
mized while maintaining an acceptable clock delay.
Figure 9. Block Diagram of I/O Cell
D
Q
RES
E
G
O
G
Slew
Rate
Control
C
I/O
From
Output PIM
To Routing
Channel
OE Mux
Register Input
Mux
Register Enable
Mux
Output Mux
Clock Mux
Clock
Polarity
Mux
Register Reset
Mux
Input
Mux
Bus
Hold
C
D
Q
RES
C
Registered OE
Mux
C
C
C
3
C
3
C
2
3
C
C
C
相關PDF資料 |
PDF描述 |
|---|---|
| CYP15G0101 | Single-channel HOTLink Transceiver |
| CYP15G0101DXB | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBC | Single-channel HOTLink Transceiver |
| CYP15G0101DXB-BBI | Single-channel HOTLink Transceiver |
| CYPOSIC2GVC-K | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| CYP15G0403DXB_07 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II⑩ Transceiver |
| CYP15G0403DXB_09 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver |
| CYP15G0403DXB_11 | 制造商:CYPRESS 制造商全稱:Cypress Semiconductor 功能描述:Independent Clock Quad HOTLink II Transceiver Single 3.3V supply |
| CYP15G0403DXB-BGC | 功能描述:電信線路管理 IC Quad Indep Channel XCVR COM RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
| CYP15G0403DXB-BGI | 功能描述:電信線路管理 IC Quad Indep Channel XCVR IND RoHS:否 制造商:STMicroelectronics 產品:PHY 接口類型:UART 電源電壓-最大:18 V 電源電壓-最小:8 V 電源電流:30 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:VFQFPN-48 封裝:Tray |
發(fā)布緊急采購，3分鐘左右您將得到回復。