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參數(shù)資料
| 型號： | CYP15G0403DXB |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設(shè)備 |
| 文件頁數(shù)： | 39/78頁 |
| 文件大?。?/td> | 1555K |
| 代理商： | CYP15G0403DXB |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 39 of 78
Channel Interconnect Parameters
t
CHSW
Adder for a signal to switch from a horizontal to vertical channel and vice-versa
t
CL2CL
Cluster to Cluster delay adder (through channels and channel PIM)
Miscellaneous Parameters
t
CPLD
Delay from the input of a cluster PIM, through a macrocell in the cluster, back to a cluster
PIM input. This parameter can be added to the t
and t
parameters for each extra
pass through the AND/OR array required by a given signal path
t
MCCD
Adder for carry chain logic per macrocell
PLL Parameters
t
MCCJ
Maximum cycle to cycle jitter time
t
DWSA
PLL delay with skew adjustment
t
DWOSA
PLL delay without any skew adjustment
t
LOCK
Lock time for the PLL
f
PLLO[18]
Output frequency of the PLL
f
PLLI[18]
Input frequency of the PLL
Note:
18. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
1.0
2.0
ns
ns
3.0
ns
0.25
ns
0.50
0.35
0.35
3.0
266
133
ns
ns
ns
ms
MHz
MHz
6.2
25
Cluster Memory Timing Parameter Values
Description
200
Parameter
Asynchronous Mode Parameters
t
CLMAA
Cluster memory access time. Delay from address change to read data out
t
CLMPWE
Write enable pulse width
t
CLMSA
Address set-up to the beginning of write enable
t
CLMHA
Address hold after the end of write enable with both signals from the same I/O block
t
CLMSD
Data set-up to the end of write enable
t
CLMHD
Data hold after the end of write enable
Synchronous Mode Parameters
t
CLMCYC1
Clock cycle time for flow-through read and write operations (from macrocell regis-
ter through cluster memory back to a macrocell register in the same cluster)
t
CLMCYC2
Clock cycle time for pipelined read and write operations (from cluster memory input
register through the memory to cluster memory output register)
t
CLMS
Address, data, and WE set-up time of pin inputs, relative to a global clock
t
CLMH
Address, data, and WE hold time of pin inputs, relative to a global clock
t
CLMDV1
Global clock to data valid on output pins for flow through data
t
CLMDV2
Global clock to data valid on output pins for pipelined data
t
CLMMACS1
Cluster memory input clock to macrocell clock in the same cluster
t
CLMMACS2
Cluster memory output clock to macrocell clock in the same cluster
t
MACCLMS1
Macrocell clock to cluster memory input clock in the same cluster
t
MACCLMS2
Macrocell clock to cluster memory output clock in the same cluster
t
CLMCLAA
Asynchronous cluster memory access time from input of cluster to output of cluster
Min.
Max.
Unit
11
ns
ns
ns
ns
ns
ns
6.0
2.0
1.0
6.0
0.5
10
ns
5.0
ns
3.0
0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
7.5
8.0
5.0
4.0
6.5
6.0
Switching Characteristics
Timing Parameter Values
(continued)
Parameter
Description
200
Min.
Max.
Unit
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