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參數(shù)資料
| 型號： | CYP15G0403DXB |
| 英文描述： | Physical Layer Devices |
| 中文描述： | 物理層設備 |
| 文件頁數(shù)： | 38/78頁 |
| 文件大小： | 1555K |
| 代理商： | CYP15G0403DXB |
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CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 38 of 78
Switching Characteristics
Timing Parameter Values
Parameter
Combinatorial Mode Parameters
Delay from any pin input, through any cluster on the channel associated with that pin input,
to any pin output on the horizontal or vertical channel associated with that cluster
t
EA
Global control to output enable
t
ER
Global control to output disable
Asynchronous macrocell RESET or PRESET recovery time from any pin input on the
horizontal or vertical channel associated with the cluster the macrocell is in
Asynchronous macrocell RESET or PRESET from any pin input on the horizontal or
vertical channel associated with the cluster that the macrocell is in to any pin output on
those same channels
Asynchronous macrocell RESET or PRESET minimum pulse width, from any pin input to
a macrocell in the farthest cluster on the horizontal or vertical channel the pin is associated
with
Synchronous Clocking Parameters
Set-up time of any input pin to a macrocell in any cluster on the channel associated with
that input pin, relative to a global clock
Hold time of any input pin to a macrocell in any cluster on the channel associated with
that input pin, relative to a global clock
Global clock to output of any macrocell to any output pin on the horizontal or vertical
channel associated with the cluster that macrocell is in
Set-up time of any input pin to the I/O cell register associated with that pin, relative to a
global clock
Hold time of any input pin to the I/O cell register associated with that pin, relative to a
global clock
t
IOCO
Clock to output of an I/O cell register to the output pin associated with that register
t
SCS
Macrocell clock to macrocell clock through array logic within the same cluster
Macrocell clock to macrocell clock through array logic in different clusters on the same
channel
I/O register clock to any macrocell clock in a cluster on the channel the I/O register is
associated with
Macrocell clock to any I/O register clock on the horizontal or vertical channel associated
with the cluster that the macrocell is in
t
CHZ
Clock to output disable (high-impedance)
t
CLZ
Clock to output enable (low-impedance)
f
MAX
Maximum frequency with internal feedback
—
within the same cluster
Maximum frequency with internal feedback
—
within different clusters at the opposite ends
of a horizontal or vertical channel
Product Term Clocking Parameters
t
MCSPT
Set-up time for macrocell used as input register, from input to product term clock
t
MCHPT
Hold time of macrocell used as an input register
t
MCCOPT
Product term clock to output delay from input pin
t
SCS2PT
Register to register delay through array logic in different clusters on the same channel us-
ing a product term clock
Description
200
Min.
Max.
Unit
t
PD
7.5
ns
5.0
5.0
ns
ns
ns
t
PRR
6.0
t
PRO
10
ns
t
PRW
3.6
ns
t
MCS
3.0
ns
t
MCH
0.0
ns
t
MCCO
6.0
ns
t
IOS
1.0
ns
t
IOH
1.0
ns
4.0
ns
ns
ns
4.0
5.0
t
SCS2
t
ICS
5.0
ns
t
OCS
5.0
ns
3.5
ns
ns
MHz
MHz
2.0
250
200
f
MAX2
3.0
1.0
ns
ns
ns
ns
8.0
6.5
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