參數(shù)資料
型號(hào)： CYP15G0403DXB
英文描述： Physical Layer Devices
中文描述： 物理層設(shè)備
文件頁(yè)數(shù)： 13/78頁(yè)
文件大?。?/td> 1555K
代理商： CYP15G0403DXB
CYP15G04K100V1-MGC
CYP15G04K200V2-MGC
PRELIMINARY
Document #: 38-02044 Rev **
Page 13 of 78
Spread Aware
PLL
Each device in the PSI family features an on-chip PLL de-
signed using Spread Aware
technology for low EMI applica-
tions. In general, PLLs are used to implement time-division-
multiplex circuits to achieve higher performance with fewer de-
vice resources.
For example, a system that operates on a 32-bit data path that
runs at 40 MHz can be implemented with 16-bit circuitry that
runs internally at 80 MHz. PLLs can also be used to take ad-
vantage of the positioning of the internally generated clock
edges to shift performance towards improved setup, hold or
clock-to-out times.
There are several frequency multiply (X1, X2, X4, X8) and di-
vide (/1, /2, /3, /4, /5, /6. /8, /16)
options available to create a
wide range of clock frequencies from a single clock input
(GCLK[0]). For increased flexibility, there are seven phase
shifting options which allow clock skew/de-skew by 45
°
, 90
°
,
135
°
, 180
°
, 225
°
, 270
°
or 315
°
.
The Spread Aware feature refers to the ability of the PLL to
track a spread-spectrum input clock such that its spread is
seen on the output clock with the PLL staying locked. The total
amount of spread on the input clock should be limited to 0.6%
of the fundamental frequency. Spread Aware feature is sup-
ported only with X1, X2 and X4 multiply options.
The Voltage Controlled Oscillator (VCO), the core of the PSI
PLL is designed to operate within the frequency range of 100
MHz to 266 MHz. Hence, the multiply option combined with
input (GCLK[0]) frequency should be selected such that this
VCO operating frequency requirement is met. This is demon-
strated in
Table 4
(columns 1, 2, and 3).
Another feature of this PLL is the ability to drive the output
clock (INTCLK) off the PSI chip to clock other devices on the
board, as shown in
Figure 11
below. This off-chip clock is half
the frequency of the output clock as it has to go through a
register (I/O register or a macrocell register).
This PLL can also be used for board deskewing purpose by
driving a PLL output clock off-chip, routing it to the other devic-
es on the board and feeding it back to the PLL
’
s external feed-
back input (GCLK[1]). When this feature is used, only limited
multiply, divide and phase shift options can be used.
Table 4
describes the valid multiply and divide options that can
be used without an external feedback.
Table 5
describes the
valid multiply & divide options that can be used with an exter-
nal feedback.
Figure 10. Block Diagram of Spread Aware PLL for CYS25G01K100
G
GCLK0
GCLK1
fb
Source
Clock
Clock Tree
Delay
Lock
PLL
X1, X2, X4, X8
GCLK0
GCLK1
TXCLK
INTCLK0
INTCLK1
INTCLK2
Normal I/O signal path
Lock Detect/IO pin
Any Register
INTCLK0, INTCLK1, INTCLK2, INTCLK3
Send a global
clock off chip
C
C
C
C
C
C
Clk 0
0
Clk 90
0
Clk 180
0
Clk 270
0
Clk 225
0
Clk 135
0
Clk 45
0
Clk 315
0
Divide
÷
1-6,8,16
RXCLK
INTCLK3
2
2
2
2
2
fb
off-chip signal (external feedback)
Phase selection
Phase selection
Phase selection
Phase selection
Divide
÷
1-6,8,16
Divide
÷
1-6,8,16
Divide
÷
1-6,8,16
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