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參數(shù)資料
| 型號： | COP8SDR9 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲器的帶32K存儲器，虛擬EEPROM和電壓過低復(fù)位的微控制器) |
| 中文描述： | 8位CMOS閃存為基礎(chǔ)的32K的內(nèi)存，虛擬EEPROM和欠壓（8位基于的CMOS閃速存儲器的帶32K的存儲器，微控制器虛擬的EEPROM和電壓過低復(fù)位的微控制器） |
| 文件頁數(shù)： | 37/68頁 |
| 文件大小： | 714K |
| 代理商： | COP8SDR9 |
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8.0 USART
(Continued)
8.1 USART CONTROL AND STATUS REGISTERS
The operation of the USART is programmed through three
registers: ENU, ENUR and ENUI.
8.2 DESCRIPTION OF USART REGISTER BITS
ENU—USART CONTROL AND STATUS REGISTER
(Ad-
dress at 0BA)
PEN
PSEL1
XBIT9/
PSEL0
CHL1
CHL0
ERR
RBFL
TBMT
Bit 7
PEN:
This bit enables/disables Parity (7- and 8-bit modes
only). Read/Write, cleared on reset.
PEN = 0
Parity disabled.
PEN = 1
Parity enabled.
PSEL1, PSEL0:
Parity select bits. Read/Write, cleared on
reset.
PSEL1 = 0, PSEL0 = 0
Odd Parity (if Parity enabled)
PSEL1 = 0, PSEL1 = 1
Even Parity (if Parity enabled)
PSEL1 = 1, PSEL0 = 0
Mark(1) (if Parity enabled)
PSEL1 = 1, PSEL1 = 1
Space(0) (if Parity enabled)
XBIT9/PSEL0:
Programs the ninth bit for transmission when
the USART is operating with nine data bits per frame. For
seven or eight data bits per frame, this bit in conjunction with
PSEL1 selects parity. Read/Write, cleared on reset.
CHL1, CHL0:
These bits select the character frame format.
Parity is not included and is generated/verified by hardware.
Read/Write, cleared on reset.
CHL1 = 0, CHL0 = 0
The frame contains eight data bits.
CHL1 = 0, CHL0 = 1
The frame contains seven data
bits.
CHL1 = 1, CHL0 = 0
The frame contains nine data bits.
CHL1 = 1, CHL0 = 1
Loopback Mode selected. Trans-
mitter output internally looped back
to receiver input. Nine bit framing
format is used.
ERR:
This bit is a global USART error flag which gets set if
any or a combination of the errors (DOE, FE, PE, BO) occur.
Read only; it cannot be written by software, cleared on reset.
RBFL:
This bit is set when the USART has received a
complete character and has copied it into the RBUF register.
It is automatically reset when software reads the character
from RBUF. Read only; it cannot be written by software,
cleared on reset.
TBMT:
This bit is set when the USART transfers a byte of
data from the TBUF register into the TSFT register for trans-
mission. It is automatically reset when software writes into
the TBUF register. Read only, bit is set to “one” on reset; it
cannot be written by software.
ENUR—USART RECEIVE CONTROLAND STATUS REG-
ISTER
(Address at 0BB)
Bit 0
DOE
Bit 7
DOE:
Flags a Data Overrun Error. Read only, cleared on
read, cleared on reset.
DOE = 0
Indicates no Data Overrun Error has been de-
tected since the last time the ENUR register
was read.
FE
PE
BD
RBIT9
ATTN
XMTG
RCVG
Bit 0
DOE = 1
Indicates the occurrence of a Data Overrun
Error.
FE:
Flags a Framing Error. Read only, cleared on read,
cleared on reset.
FE = 0
Indicates no Framing Error has been detected
since the last time the ENUR register was read.
FE = 1
Indicates the occurrence of a Framing Error.
PE:
Flags a Parity Error. Read only, cleared on read, cleared
on reset.
PE = 0
Indicates no Parity Error has been detected since
the last time the ENUR register was read.
PE = 1
Indicates the occurrence of a Parity Error.
BD:
Flags a line break.
BD = 0 Indicates no Line Break has been detected since
the last time the ENUR register was read.
BD = 1 Indicates the occurrence of a Line Break.
RBIT9:
Contains the ninth data bit received when the
USART is operating with nine data bits per frame. Read only,
cleared on reset.
ATTN:
ATTENTION Mode is enabled while this bit is set.
This bit is cleared automatically on receiving a character with
data bit nine set. Read/Write, cleared on reset.
XMTG:
This bit is set to indicate that the USART is transmit-
ting. It gets reset at the end of the last frame (end of last Stop
bit). Read only, cleared on reset.
RCVG:
This bit is set high whenever a framing error occurs
and goes low when RDX goes high. Read only, cleared on
reset.
ENUI—USART INTERRUPT AND CLOCK SOURCE REG-
ISTER
(Address at 0BC)
STP2
Bit 7
STP2:
This bit programs the number of Stop bits to be
transmitted. Read/Write, cleared on reset.
STP2 = 0
One Stop bit transmitted.
STP2 = 1
Two Stop bits transmitted.
BRK:
Holds TDX (USART Transmit Pin) low to generate a
Line Break. Timing of the Line Break is under software
control.
ETDX:
TDX (USART Transmit Pin) is the alternate function
assigned to Port L pin L2; it is selected by setting ETDX bit.
SSEL:
USART mode select. Read only, cleared on reset.
SSEL = 0
Asynchronous Mode.
SSEL = 1
Synchronous Mode.
XRCLK:
This bit selects the clock source for the receiver
section. Read/Write, cleared on reset.
XRCLK = 0
The clock source is selected through the
PSR and BAUD registers.
XRCLK = 1
Signal on CKX (L1) pin is used as the clock.
XTCLK:
This bit selects the clock source for the transmitter
section. Read/Write, cleared on reset.
XTCLK = 0
The clock source is selected through the
PSR and BAUD registers.
XTCLK = 1
Signal on CKX (L1) pin is used as the clock.
ERI:
This bit enables/disables interrupt from the receiver
section. Read/Write, cleared on reset.
ERI = 0
Interrupt from the receiver is disabled.
ERI = 1
Interrupt from the receiver is enabled.
BRK
ETDX
SSEL
XRCLK
XTCLK
ERI
ETI
Bit 0
C
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