參數(shù)資料
型號: COP8SDR9
廠商: National Semiconductor Corporation
英文描述: 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲器的帶32K存儲器,虛擬EEPROM和電壓過低復(fù)位的微控制器)
中文描述: 8位CMOS閃存為基礎(chǔ)的32K的內(nèi)存,虛擬EEPROM和欠壓(8位基于的CMOS閃速存儲器的帶32K的存儲器,微控制器虛擬的EEPROM和電壓過低復(fù)位的微控制器)
文件頁數(shù): 29/68頁
文件大?。?/td> 714K
代理商: COP8SDR9
7.0 Power Saving Features
Today, the proliferation of battery-operated applications has
placed new demands on designers to drive power consump-
tion down. Battery operated systems are not the only type of
applications demanding low power. The power budget con-
straints are also imposed on those consumer/industrial ap-
plications where well regulated and expensive power supply
costs cannot be tolerated. Such applications rely on low cost
and low power supply voltage derived directly from the
“mains” by using voltage rectifier and passive components.
Low power is demanded even in automotive applications,
due to increased vehicle electronics content. This is required
to ease the burden from the car battery. Low power 8-bit
microcontrollers supply the smarts to control battery-
operated, consumer/industrial, and automotive applications.
The device offers system designers a variety of low-power
consumption features that enable them to meet the demand-
ing requirements of today’s increasing range of low-power
applications. These features include low voltage operation,
low current drain, and power saving features such as HALT,
IDLE, and Multi-Input walk-up (MIWU).
This device supports three operating modes, each of which
have two power save modes of operation. The three operat-
ing modes are: High Speed, Dual Clock, and Low Speed.
Within each operating mode, the two power save modes are:
HALT and IDLE. In the HALT mode of operation, all micro-
controller activities are stopped and power consumption is
reduced to a very low level. In this device, the HALT mode is
enabled and disabled by a bit in the Option register. The
IDLE mode is similar to the HALT mode, except that certain
sections of the device continue to operate, such as: the
on-board oscillator, the IDLE Timer (Timer T0), and the Clock
Monitor. This allows real time to be maintained. During
power save modes of operation, all on board RAM, registers,
I/O states and timers (with the exception of T0) are unal-
tered.
Two oscillators are used to support the three different oper-
ating modes. The high speed oscillator refers to the oscillator
connected to CKI and the low speed oscillator refers to the
32 kHz oscillator connected to pins L0 & L1. When using L0
and L1 for the low speed oscillator, the user must ensure that
the L0 and L1 pins are configured for hi-Z input, L1 is not
using CKX on the USART, and Multi-Input-Walk-up for these
pins is disabled.
A diagram of the three modes is shown in Figure 18
7.1 POWER SAVE MODE CONTROL REGISTER
The ITMR control register allows for navigation between the
three different modes of operation. It is also used for the Idle
Timer. The register bit assignments are shown below. This
register is cleared to 40 (hex) by Reset as shown below.
LSON
HSON
DCEN
CCK
SEL
RSVD
ITSEL2
ITSEL1
ITSEL0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
LSON:
This bit is used to turn-on the low-speed oscil-
lator. When LSON = 0, the low speed oscillator
is off. When LSON = 1, the low speed oscillator
is on. There is a startup time associated with
this oscillator. See the Oscillator Circuits sec-
tion.
This bit is used to turn-on the high speed oscil-
lator. When HSON = 0, the high speed oscillator
HSON:
is off. When HSON = 1, the high speed oscillator
is on. There is a startup time associated with
this oscillator. See the startup time table in the
Oscillator Circuits section.
This bit selects the clock source for the Idle
Timer. If this bit = 0, then the high speed clock is
the clock source for the Idle Timer. If this bit = 1,
then the low speed clock is the clock source for
the Idle Timer. The low speed oscillator must be
started and stabilized before setting this bit to a
1.
This bit selects whether the high speed clock or
low speed clock is gated to the microcontroller
core. When this bit = 0, the Core clock will be
the high speed clock. When this bit = 1, then the
DCEN:
CCKSEL:
DS101389-22
FIGURE 18. Diagram of Power Save Modes
C
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29
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