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參數(shù)資料
| 型號： | COP8SDR9 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout(8位基于CMOS 閃速存儲器的帶32K存儲器，虛擬EEPROM和電壓過低復位的微控制器) |
| 中文描述： | 8位CMOS閃存為基礎(chǔ)的32K的內(nèi)存，虛擬EEPROM和欠壓（8位基于的CMOS閃速存儲器的帶32K的存儲器，微控制器虛擬的EEPROM和電壓過低復位的微控制器） |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 714K |
| 代理商： | COP8SDR9 |
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6.0 Timers
The device contains a very versatile set of timers (T0, T1, T2
and T3). Timers T1, T2 and T3 and associated autoreload/
capture registers power up containing random data.
6.1 TIMER T0 (IDLE TIMER)
The device supports applications that require maintaining
real time and low power with the IDLE mode. This IDLE
mode support is furnished by the IDLE Timer T0, which is a
16-bit timer. The user cannot read or write to the IDLE Timer
T0, which is a count down timer.
As described in 7.0 Power Saving Features the clock to the
IDLE Timer depends on which mode the device is in. If the
device is in High Speed mode, the clock to the IDLE Timer is
the instruction cycle clock (one-fifth of the CKI frequency). If
the device is in Dual Clock mode or Low Speed mode, the
clock to the IDLE Timer is the 32 kHz clock. For the remain-
der of this section, the term “selected clock” will refer to the
clock selected by the Power Save mode of the device.
During Dual Clock and Low Speed modes, the divide by 10
that creates the instruction cycle clock is disabled, to mini-
mize power consumption.
In addition to its time base function, the Timer T0 supports
the following functions:
Exit out of the Idle Mode (See Idle Mode description)
Figure 14is a functional block diagram showing the structure
of the IDLE Timer and its associated interrupt logic.
Bits 11 through 15 of the ITMR register can be selected for
triggering the IDLE Timer interrupt. Each time the selected
bit underflows (every 4k, 8k, 16k, 32k or 64k selected
clocks), the IDLE Timer interrupt pending bit T0PND is set,
thus generating an interrupt (if enabled), and bit 6 of the Port
G data register is reset, thus causing an exit from the IDLE
mode if the device is in that mode.
In order for an interrupt to be generated, the IDLE Timer
interrupt enable bit T0EN must be set, and the GIE (Global
Interrupt Enable) bit must also be set. The T0PND flag and
T0EN bit are bits 5 and 4 of the ICNTRL register, respec-
tively. The interrupt can be used for any purpose. Typically, it
is used to perform a task upon exit from the IDLE mode. For
more information on the IDLE mode, refer to 7.0 Power
Saving Features
The Idle Timer period is selected by bits 0–2 of the ITMR
register Bit 3 of the ITMR Register is reserved and should
not be used as a software flag. Bits 4 through 7 of the ITMR
Register are used by the dual clock and are described in 7.0
Power Saving Features
WATCHDOG logic (See WATCHDOG description)
Start up delay out of the HALT mode
Start up delay from BOR
TABLE 15. Idle Timer Window Length
ITSEL2 ITSEL1 ITSEL0
Idle Timer Period
High Speed
Mode
4,096 inst. cycles
8,192 inst. cycles
16,384 inst. cycles
32,768 inst. cycles
65,536 inst. cycles
Reserved - Undefined
Reserved - Undefined
Reserved - Undefined
Dual Clock or
Low Speed Mode
0.125 seconds
0.25 seconds
0.5 seconds
1 second
2 seconds
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
The ITSEL bits of the ITMR register are cleared on Reset
and the Idle Timer period is reset to 4,096 instruction cycles.
ITMR Register
LSON
HSON
DCEN
CCK
SEL
Bit 4
RSVD
ITSEL2
ITSEL1
ITSEL0
Bit 7
Bits 7–4:
Described in 7.0 Power Saving Features
Note: Documentation for previous COP8 devices, which in-
cluded the Programmable Idle Timer, recommended the user
write zero to the high order bits of the ITMR Register. If
existing programs are updated to use this device, writing
zero to these bits will cause the device to reset (see 7.0
Power Saving Features).
RSVD:
This bit is reserved and must be set to 0.
ITSEL2:0:
Selects the Idle Timer period as described in
Table 15, Idle Timer Window Length.
Any time the IDLE Timer period is changed there is the
possibility of generating a spurious IDLE Timer interrupt by
setting the T0PND bit. The user is advised to disable IDLE
Bit 6
Bit 5
Bit 3
Bit 2
Bit 1
Bit 0
DS101389-18
FIGURE 14. Functional Block Diagram for Idle Timer T0
C
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| COP8SDR9HLQ7 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:8-Bit CMOS Flash Based Microcontroller with 32k Memory, Virtual EEPROM and Brownout |
| COP8SDR9HLQ8 | 功能描述:IC MCU FLASH 8BIT 32K EE 44LLP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:COP8™ 8S 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
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| COP8SDR9HVA8 | 功能描述:8位微控制器 -MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
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