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參數(shù)資料
| 型號(hào)： | CN8223EPF |
| 英文描述： | ATM/SONET TRANSCEIVER|CMOS|QFP|160PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的收發(fā)器|的CMOS | QFP封裝| 160PIN |塑料 |
| 文件頁(yè)數(shù)： | 79/161頁(yè) |
| 文件大?。?/td> | 1865K |
| 代理商： | CN8223EPF |
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DS3 Terminal Data Link C bits
G.751 E3 N bit
G.832 E3 and E4 GC octet
STS-1/STS-3c/STM-1 D1, D2, D3 octet data link
CN8223
2.0 Functional Description
ATM Transmitter/Receiver with UTOPIA Interface
2.8 FEAC Channel and HDLC Data Link Programming
100046D
Conexant
2-45
2.8.2 FEAC Channel Receiver
The FEAC channel receiver is under control only of the received data stream. The
receiver interrupt is under control of Enable Receive FEAC Interrupt [bit 8] in
TXFEAC_ERRPAT. This interrupt must be enabled by setting this bit for receiver
interrupts to appear on the DL_INT output and for proper interaction with the
processor. The last C bit in subframe 1 in C bit parity mode is provided to the
receiver circuitry at all times.
Receiver status is monitored via Receive FEAC Interrupt [bit 9] in
RXFEAC_VER. When a receive FEAC channel interrupt is generated on
DL_INT, the Receive FEAC Interrupt bit will be set in 0x3C. If this bit is
observed upon reading the RXFEAC_VER, then at least 10 repetitions of the
same byte have been received by the data link and placed in bits 15
–
10 of
RXFEAC_VER. The receive interrupt serves as notice that the message bits in
RXFEAC_VER are valid. Reading RXFEAC_VER clears the receive interrupt.
An idle message is all 1s, and all other messages are of the form
“
0xxxmmm011111111
”
with reception of the rightmost bit first from the
channel. The receiver logic recognizes the eight 1s message flag followed by a
message byte and interrupts the controller upon reception of 10 repetitions of a
valid message byte. The
“
mmmxxx
”
message byte that was received is stored in
RXFEAC_VER bits 15
–
10 at 0x3C. Continuous incoming messages on the
FEAC channel produce an interrupt rate of approximately one interrupt per 17 ms
for this interrupt source. No interrupts are generated if the FEAC channel is
receiving continuous idle flags or if the interrupt is not enabled in
TXFEAC_ERRPAT.
2.8.3 HDLC Data Link Transmitter
The HDLC data link capability is present in the following formats:
The HDLC formatter has an 8-octet buffer (organized as four 16-bit words)
for both the receiver and transmitter, located at addresses 0x58 through 0x5B and
0x5C through 0x5F, respectively. Addresses are word-wide locations that hold 2
bytes each. Therefore, each buffer has an address range of 4, two for each buffer
half. Each buffer holds 4 octets.
The HDLC data link transmitter is under the control of the Enable HDLC Data
Link [bit 5] in the CONFIG_5 [0x31] and bits 6
–
0 in DL_CTRL_STAT [0x60].
An interrupt for use with data link operations is available on the DL_INT output
pin, and status bits for determining the interrupt source are located in
DL_CTRL_STAT.
If the framer is in a mode that allows data link transmission as described
above, the DL_CTRL_STAT register is the main control register used for transmit
data link operations. Disable Data Link Transmission [bit 6] of DL_CTRL_STAT
must be set low to enable operation of the data link. If this bit is set high, an all 1s
signal is transmitted in the data link bit positions in the outgoing serial stream.
With the data link enabled, the Send Message [bit 0], Send FCS [bit 1], and Abort
Message [bit 2] bits of DL_CTRL_STAT control operation. TxBytes[2:0] [bits
5
–
3] of DL_CTRL_STAT form a pointer to the TX_DL_BUFFER used by the
data link transmitter.
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