參數(shù)資料
型號： CN8223EPF
英文描述： ATM/SONET TRANSCEIVER|CMOS|QFP|160PIN|PLASTIC
中文描述： 的ATM / SONET的收發(fā)器|的CMOS | QFP封裝| 160PIN |塑料
文件頁數(shù)： 23/161頁
文件大小： 1865K
代理商： CN8223EPF
The G1 octet complies with T1.105. The RDI alarm includes bit 7.
The K1/K2 registers were added to provide further support for SONET APS.
HEC integration was removed.
The device complies with a footnote in the UTOPIA specification that allows RxENB~ to be
permanently asserted by the ATM layer.
Disable HEC Check (bit 9 in CELL_VAL) was changed when in UTOPIA mode to be consistent
with FIFO mode.
Payload checking will comply with the ATM standards (lengths 8-44).
When switching to PLCP mode dynamically, the device will go to an OOF state.
FIFO read strobes are forced inactive (high) during hardware or software resets.
CN8223
1.0 Product Description
ATM Transmitter/Receiver with UTOPIA Interface
1.7 CN8223 Versions
100046D
Conexant
1-13
1.7 CN8223 Versions
Table 1-1
describes the revision history of the Bt8222 device. The Bt8222 is the
predecessor of the CN8223.
Table 1-1. CN8223 Version Descriptions
Version
Description
Bt8222KPF
Baseline version (derived from the Bt8220/1).
Bt8222KPFB
All Bt8222KPF functionality plus:
The version number was changed to 62H in the lower byte of the RX_FEAC_VER register.
A software reset was added to CONFIG_5, bit 7. When active high, this is a software equivalent
to pin 118.
Additional overhead insertion capability for STS-3c, STM-1: G1, K2 #1, and Z2 #3 can be
inserted from the external overhead bus. It is controlled by CONFIG_3, bit 6. This is used for
automatic protection switching.
CONFIG_5 has a new receive status indication. CONFIG_5, bit 9 now shows octet G1, bit 5 of
received frames.
Bt8222KPFC
All Bt8222KPFB functionality plus:
The version number was changed to 63H in the lower byte of the RX_FEAC_VER register.
The STM-1 C2 transmit octet = 0x13. The C2 receive octet is checked for 0x01 or 0x13.
Bt8222KPFD or
Bt8222EPFD
All Bt8222KPFC functionality plus:
The version number was changed to 64H in the lower byte of the RX_FEAC_VER register.
TAXI command strobe timing eliminates the need for an external buffer.
Bt8222EPFE
All Bt8222KPFD/EPFD functionality plus:
RMRKR[1] was changed to be an 8 kHz output synchronized to the received PLCP frame.
Bt8222EPFF
All Bt8222EPFE functionality plus:
Line Loopback (bit 9) in the CONFIG_3 register (0x02) is cleared upon assertion of RESET (pin
118).
Receive STS/SDH pointer processing complies with standards.
Legend for Version Numbers:
K = Temperature range 0
°
C to 70
°
C
E =
–
40
°
C to 85
°
C
PF = Package code = 160-pin PQFP
A/B/C/D/E = Product version
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