參數(shù)資料
型號： CN8223EPF
英文描述： ATM/SONET TRANSCEIVER|CMOS|QFP|160PIN|PLASTIC
中文描述： 的ATM / SONET的收發(fā)器|的CMOS | QFP封裝| 160PIN |塑料
文件頁數(shù)： 132/161頁
文件大小： 1865K
代理商： CN8223EPF
3
C
3
A
3
C
1
Disable Port Reception - Port 0
Disable Port Reception - Port 1
Disable Port Reception - Port 2
Disable Port Reception - Port 3
F
IDLE_PAY (0x2A)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Idle Cell Payload Octet
Enable Idle Cell CRC Insertion
Reserved
TXFEAC_ERRPAT (0x03)
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Error Insertion Pattern
Enable Receive FEAC Interrupt
Transmit FEAC Data
Enable FEAC Transmission
CELL_GEN_x (0x04–0x07)
15 14 13 12 11 10 9
8
7
6 5
4
3
2
1
0
Error Payload CRC
Error HEC
Disable Payload CRC
Disable HEC
Insert CLP
Insert PT
Insert VCI
Port Priority
Insert GFC
Insert VPI
Reserved
Cell Generation Mode
1 0
0 0 48 Octet
1 0 53 Octet
1 1 57 Octet
Header and Mask Registers (0x15–0x1C, 0x1D–0x24)
15 14 13 12 11 10 9
8
7 6
5
4
3 2
1
0
Header Octet 1
Header Octet 2
15 14 13 12 11 10 9
8
7 6
5
4
3 2
1
0
Header Octet 3
Header Octet 4
CONFIG_5 (0x31)
15 14 13 12 11 10 9
8
7
6 5
4
3
2
1
0
Reserved
HEC OCD Anomaly
Receive G1 Bit 5
Receive G1 Bit 6
Software Reset
Transmit Clock Select
Enable External Signal Label
Transmit G1 Bit 6
Transmit G1 Bit 5
Integrate HEC Framing
Enable HDLC Data Link
Set G1 X Bits All Ones
External 8-kHz Timing
Receiver Hold Enable
Enable Parallel Interface
Enable HEC Alignment
Disable LOCD
Enable Cell Scrambler
Enable One-second
Latching of Line Counters
Enable One-second
Latching of Line Status
CONFIG_1 (0x00)
15 14 13 12 11 10 9
8
7
6 5
4
3
2
1
0
STS-1 Stuffing Option
Source Loopback
PHY Type
Unframed Input
Disable B3ZS/HDB3
External Framer
CONFIG_2 (0x01)
15 14 13 12 11 10 9
8
7
6 5
4
3
2
1
0
Enable External Overhead
All-zeros FEBE
All-ones FEBE
Overhead Control
Transmit Alarm Control
BIP Error Insert
CONFIG_3 (0x02)
15 14 13 12 11 10 9
8
7
6 5
4
3
2
1
0
Accept/Reject Header - Port 3
Accept/Reject Header - Port 2
Accept/Reject Header - Port 1
Accept/Reject Header - Port 0
Count Block Errors
Enable HEC Coset
HEC Coverage
Enable DS1 PRS Generator
Disable Write Strobes on Invalid Cells
Check Input Parity
Parity Odd/Even
Force Cycle Stuffing/Tx Overhead Control
Invert TX Clock Output
Reserved
Line Loopback
Invert RX Clock Sampling
CONFIG_4 (0x29)
15 14 13 12 11 10 9
8
7
6 5
4
3
2
1
0
Disable CRC Check - Port 3
Disable CRC Check - Port 2
Disable CRC Check - Port 1
Disable CRC Check - Port 0
Disable Length Check - Port 3
Disable Length Check - Port 2
Disable Length Check - Port 1
Disable Length Check - Port 0
STM-1/STS-3c Pointer
Enable External Section Trace
Delete Idle Cells
Enable TAXI Interface
Inhibit Single Cell Generation
0 - DS1
1 - E1
5 - E4
6 - STS1
7 - STS3
TX_RATE Registers (0x08, 0x09)
15 14 13 12 11 10 9
8
7 6
5
4
3 2
1
0
Rate Value - Port 2
Rate Value - Port 3
15 14 13 12 11 10 9
8
7 6
5
4
3 2
1
0
Rate Value - Port 0
Rate Value - Port 1
PHY Type
8223_031
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