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參數(shù)資料
| 型號(hào)： | CN8223EPF |
| 英文描述： | ATM/SONET TRANSCEIVER|CMOS|QFP|160PIN|PLASTIC |
| 中文描述： | 的ATM / SONET的收發(fā)器|的CMOS | QFP封裝| 160PIN |塑料 |
| 文件頁(yè)數(shù)： | 111/161頁(yè) |
| 文件大?。?/td> | 1865K |
| 代理商： | CN8223EPF |
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CN8223
3.0 Registers
ATM Transmitter/Receiver with UTOPIA Interface
3.6 Interrupt Enable Control Registers
100046D
Conexant
3-25
Enables interrupt when header of an incoming cell matches the header value
programmed in the RX_IDLE and IDLE_MSK registers.
0x2E
—
EN_EVENT_INT (Enable Event Interrupts)
The EN_EVENT_INT register is located at address 0x2E and enables interrupts for the EVENT_STATUS
register (0x39). Setting a bit in EN_EVENT_INT enables each interrupt condition to appear on STAT_INT.
Bit
Field
Size
Name
Description
15
1
Receiver Hold Input
Interrupt Enable
Indicates that an active-high input was received on the RCV_HLD input pin.
14
–
13
4
Reserved
Set to 0.
12
1
APS Interrupt
Enables interrupt when received value of the K1 or K2 byte changes in the
SONET frame.
11
1
Start of Cell Error
Indicates that a Start of Cell Alignment Error was received on the
FCTRL_IN[0] input pin (109).
10
1
Port 3 Input Parity Error
Interrupt Enable
Enables parity error interrupt from FIFO data input port 3. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
9
1
Port 2 Input Parity Error
Interrupt Enable
Enables parity error interrupt from FIFO data input port 2. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
8
1
Port 1 Input Parity Error
Interrupt Enable
Enables parity error interrupt from FIFO data input port 1. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
7
1
Port 0 Input Parity Error
Interrupt Enable
Enables parity error interrupt from FIFO data input port 0. These interrupts
and status bits will be active only if input parity checking is enabled in
CONFIG_3.
6
1
Idle Cells Interrupt Enable
5
1
Non-matching Cells
Interrupt Enable
Enables interrupt when the header of an incoming cell does not match any of
the header values programmed in the HDR_VALx and HDR_MSKx registers.
4
1
Non-zero GFC Interrupt
Enable
Enables interrupt when the 4-bit GFC field of an incoming cell header is any
value other than 0000.
3
1
Payload Length Error
Interrupt Enable
Enables interrupt when an error is detected in the 6-bit payload length field of
the cell trailer. This event is meaningful only for AAL3/4 payloads that contain
a payload length.
2
1
Payload CRC Error
Interrupt Enable
Enables interrupt when an error is detected in the 10-bit payload CRC of the
cell trailer. This event is meaningful only for AAL3/4 payloads that contain a
payload CRC.
1
1
HEC Error Not Corrected
Interrupt Enable
Enables interrupt when an uncorrectable error is detected in the HEC octet of
the cell header.
0
1
HEC Error Corrected
Interrupt Enable
Enables interrupt when an error is detected and corrected in the HEC octet of
the cell header.
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