參數(shù)資料
型號(hào)： BX805573060
廠商： INTEL CORP
元件分類： 微控制器/微處理器
英文描述： 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775
封裝： LGA-775
文件頁數(shù)： 91/102頁
文件大?。?/td> 2428K
代理商： BX805573060
Dual-Core Intel Xeon Processor 3000 Series Datasheet
89
Features
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor will return
execution to the HALT state.
While in HALT Power Down state, the processor processes bus snoops.
6.2.2.2
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed
the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor
is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its
specification.
The processor automatically transitions to a lower frequency and voltage operating
point before entering the Extended HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
While in Extended HALT state, the processor processes bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the
processor exits the Extended HALT state, it first transitions the VID to the original value
and then changes the bus ratio back to the original value.
6.2.3
Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to V
TT) for minimum power drawn by the termination
resistors in this state. In addition, all other input signals on the FSB should be driven to
the inactive state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. A transition back to the Normal state occurs with the de-assertion
of the STPCLK# signal.
A transition to the Grant Snoop state occurs when the processor detects a snoop on the
While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] is latched by the processor,
and only serviced when the processor returns to the Normal State. Only one occurrence
of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor processes a FSB snoop.
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