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參數(shù)資料
| 型號： | BX805573060 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775 |
| 封裝： | LGA-775 |
| 文件頁數(shù)： | 25/102頁 |
| 文件大?。?/td> | 2428K |
| 代理商： | BX805573060 |
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Dual-Core Intel Xeon Processor 3000 Series Datasheet
29
Electrical Specifications
2.7.3.1
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 2-9 for details on which GTL+ signals do not include on-die
termination.
Valid high and low levels are determined by the input buffers by comparing with a
reference voltage called GTLREF. Table 2-15 lists the GTLREF specifications. The GTL+
reference voltage (GTLREF) should be generated on the system board using high
precision voltage divider circuits.
2.7.4
Clock Specifications
2.7.5
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the
processor. As in previous generation processors, the processor’s core frequency is a
multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to Table 2-16 for the processor supported
ratios.
The processor uses a differential clocking implementation. For more information on the
processor clocking, contact your Intel Field representative. Platforms using a CK505
Clock Synthesizer/Driver should comply with the specifications in Section 2.7.8.
Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications
Table 2-15. GTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes1
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
GTLREF_PU
GTLREF pull up resistor
124 * 0.99
124
124 * 1.01
Ω
2
2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land).
GTLREF_PD
GTLREF pull down resistor
210 * 0.99
210
210 * 1.01
Ω
RTT
Termination Resistance
45
50
55
Ω
3
3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver.
COMP[3:0]
COMP Resistance
49.40
49.90
50.40
Ω
4
4. COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design
guide for implementation details. COMP[3:0] and COMP8 resistors are tied to VSS.
COMP8
COMP Resistance
24.65
24.90
25.15
Ω
Table 2-16. Core Frequency to FSB Multiplier Configuration
Multiplication of System Core
Frequency to FSB Frequency
Core Frequency
(266 MHz BCLK/1066 MHz FSB)
Notes1, 2
Notes:
1. Individual processors operate only at or below the rated frequency.
2. Listed frequencies are not necessarily committed production frequencies.
1/6
1.60 GHz
-
1/7
1.87 GHz
-
1/8
2.13 GHz
-
1/9
2.40 GHz
-
1/10
2.66 GHz
-
1/11
2.93 GHz
-
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