- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄223478 > BX805573060 (INTEL CORP) 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775 PDF資料下載
參數(shù)資料
| 型號(hào)： | BX805573060 |
| 廠商： | INTEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 64-BIT, 2400 MHz, MICROPROCESSOR, CBGA775 |
| 封裝： | LGA-775 |
| 文件頁數(shù)： | 68/102頁 |
| 文件大?。?/td> | 2428K |
| 代理商： | BX805573060 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁當(dāng)前第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁
Land Listing and Signal Descriptions
68
Dual-Core Intel Xeon Processor 3000 Series Datasheet
DEFER#
Input
DEFER# is asserted by an agent to indicate that a transaction cannot
be ensured in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or input/output agent. This
signal must connect the appropriate pins/lands of all processor FSB
agents.
DRDY#
Input/Output
DRDY# (Data Ready) is asserted by the data driver on each data
transfer, indicating valid data on the data bus. In a multi-common
clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]#
Input/Output
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
DSTBP[3:0]#
Input/Output
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
FCx
Other
FC signals are signals that are available for compatibility with other
processors.
FERR#/PBE#
Output
FERR#/PBE# (floating point error/pending break event) is a
multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error
and will be asserted when the processor detects an unmasked
floating-point error. When STPCLK# is not asserted, FERR#/PBE# is
similar to the ERROR# signal on the Intel 387 coprocessor, and is
included for compatibility with systems using MS-DOS*-type floating-
point error reporting. When STPCLK# is asserted, an assertion of
FERR#/PBE# indicates that the processor has a pending break event
waiting for service. The assertion of FERR#/PBE# indicates that the
processor should be returned to the Normal state. For additional
information on the pending break event functionality, including the
identification of support of the feature and enable/disable information,
refer to volume 3 of the Intel Architecture Software Developer's
Manual and the Intel Processor Identification and the CPUID
Instruction application note.
GTLREF[1:0]
Input
GTLREF[1:0] determine the signal reference level for GTL+ input
signals. GTLREF is used by the GTL+ receivers to determine if a signal
is a logical 0 or logical 1.
HIT#
HITM#
Input/Output
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Any FSB agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be
continued by reasserting HIT# and HITM# together.
IERR#
Output
IERR# (Internal Error) is asserted by a processor as the result of an
internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may
optionally be converted to an external error signal (e.g., NMI) by
system core logic. The processor will keep IERR# asserted until the
assertion of RESET#.
This signal does not have on-die termination. Refer to Section 2.6.2
for termination requirements.
Table 4-3.
Signal Description (Sheet 3 of 7)
Name
Type
Description
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBN0#
D[31:16]#, DBI1#
DSTBN1#
D[47:32]#, DBI2#
DSTBN2#
D[63:48]#, DBI3#
DSTBN3#
Signals
Associated Strobe
D[15:0]#, DBI0#
DSTBP0#
D[31:16]#, DBI1#
DSTBP1#
D[47:32]#, DBI2#
DSTBP2#
D[63:48]#, DBI3#
DSTBP3#
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BX80562X3210SLACU | 64-BIT, 266 MHz, MICROPROCESSOR, PBGA775 |
| BX80616I5660SLBLV | 64-BIT, 133 MHz, MICROPROCESSOR, PBGA1156 |
| BXA10-48D15-S | DC to DC Converter |
| BXA10-48S05 | EMI FILTER INCLUDING ESD PROTECTION |
| BXA10-48S05-S | 8 line low capacitance EMI filter and ESD protection |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BX80557430SL9XN | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel?? Celeron?? Processor 400 Series |
| BX80557440 S L9XL | 制造商:Intel 功能描述:MPU Celeron |
| BX80557E1500 | 制造商:Intel 功能描述:INTEL CELERON PROCESSOR E15002.2GHZ 800MHZ FSB 512KB L2 |
| BX80557E1500 S LAQZ | 制造商:Intel 功能描述:INTEL CELERON PROCESSOR FAMILY E1500, 2.2 GHZ CPU SPEED |
| BX80557E1600 | 制造商:Intel 功能描述:INTEL CELERON PROCESSOR E16002.4GHZ 800MHZ FSB 512KB L2 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。