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| 型號(hào)： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器） |
| 文件頁數(shù)： | 86/121頁 |
| 文件大小： | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
82
7.9 Software interrupt and exception entry
Exceptions (and software interrupts) force the PC to a particular value and refill the instruction pipeline
from there. During the first cycle the forced address is constructed, and a mode change may take place. The
return address is moved to R14 and the CPSR to SPSR_svc.
During the second cycle the return address is modified to facilitate return, though this modification is less
useful than in the case of branch with link.
The third cycle is required only to complete the refilling of the instruction pipeline. The cycle timings are
shown below in
Table 15: Software Interrupt Instruction Cycle Operations
.
For software interrupts,
pc
is the address of the SWI instruction. For interrupts and reset,
pc
is the address
of the instruction following the last one to be executed before entering the exception. For prefetch
abort,
pc
is the address of the
aborting instruction. For data abort,
pc
is the address of the instruction following the
one which attempted the
aborted data transfer.
Xn
is the appropriate trap address.
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
LOCK
1
pc+8
1
0
(pc+8)
0
0
0
0
2
Rn
b/w
0
(Rn)
0
0
1
1
3
Rn
b/w
1
Rm
1
0
1
1
4
pc+12
1
0
-
0
1
1
0
pc+12
Table 14: Data Swap Instruction Cycle Operations
Cycle
Address
nBW
nRW
Data
nMREQ
SEQ
nOPC
nTRANS
1
pc+8
1
0
(pc+8)
0
0
0
1
2
Xn
1
0
(Xn)
0
1
0
1
3
Xn+4
1
0
(Xn+4)
0
1
0
1
Xn+8
Table 15: Software Interrupt Instruction Cycle Operations
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