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參數(shù)資料
| 型號： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡指令集微處理器） |
| 文件頁數(shù)： | 14/121頁 |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
10
ARM60 supports six modes of operation:
(1)
User mode (usr): the normal program execution state
(2)
FIQ mode (fiq): designed to support a data transfer or channel process
(3)
IRQ mode (irq): used for general purpose interrupt handling
(4)
Supervisor mode (svc): a protected mode for the operating system
(5)
Abort mode (abt): entered after a data or instruction prefetch
abort
(6)
Undefined mode (und): entered when an undefined instruction is executed
Mode changes may be made under software control or may be brought about by external interrupts or
exception processing. Most application programs will execute in User mode. The other modes, known as
privileged modes
, will be entered to service interrupts or exceptions or to access protected resources.
3.3 Registers
The processor has a total of 37 registers made up of 31 general 32 bit registers and 6 status registers. At any
one time 16 general registers (R0 to R15) and one or two status registers are visible to the programmer. The
visible registers depend on the processor mode and the other registers (the
to support IRQ, FIQ, Supervisor,
Abort and Undefined mode processing. The register bank organisation is
shown in
Figure 3: Register Organisation
. The banked registers are shaded in the diagram.
banked registers
) are switched in
In all modes 16 registers, R0 to R15, are directly accessible. All registers except R15 are general purpose and
may be used to hold data or address values. Register R15 holds the Program Counter (PC). When R15 is
read, bits [1:0] are zero and bits [31:2] contain the PC. A seventeenth register (the CPSR - Current Program
Status Register) is also accessible. It contains condition code flags and the current mode bits and may be
thought of as an extension to the PC.
R14 is used as the subroutine link register and receives a copy of R15 when a Branch and Link instruction
is executed. It may be treated as a general purpose register at all other times. R14_svc, R14_irq, R14_fiq,
R14_abt and R14_und are used similarly to hold the return values of R15 when interrupts and exceptions
arise, or when Branch and Link instructions are executed within interrupt or exception routines.
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