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| 型號(hào)： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器） |
| 文件頁數(shù)： | 20/121頁 |
| 文件大小： | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
16
3.4.6 Vector Summary
These are byte addresses, and will normally contain a branch instruction pointing to the relevant routine.
The FIQ routine might reside at 0x1C onwards, and thereby avoid the need for (and execution time of) a
branch instruction.
The reserved entry is for an Address Exception vector which is only operative when the processor is
configured for a 26 bit program space. See
13.0 Appendix - Backward Compatibility
3.4.7 Exception Priorities
When multiple exceptions arise at the same time, a fixed priority system determines the order in which they
will be handled:
(1)
Reset (highest priority)
(2)
Data abort
(3)
FIQ
(4)
IRQ
(5)
Prefetch abort
(6)
Note that not all exceptions can occur at once. Undefined instruction and software interrupt are mutually
exclusive since they each correspond to particular (non-overlapping) decodings of the current instruction.
Undefined Instruction, Software interrupt (lowest priority)
If a data abort
ARM60 will enter the data abort handler and then immediately proceed to the FIQ vector. A normal return
from FIQ will cause the data abort handler to resume execution. Placing data abort at a higher priority than
FIQ is necessary to ensure that the transfer error does not escape detection; the time for this exception entry
should be added to worst case FIQ latency calculations.
occurs at the same time as a FIQ, and FIQs are enabled (i.e. the F flag in the CPSR is clear),
Address
Exception
Mode on entry
0x00000000
Reset
Supervisor
0x00000004
UndeTned instruction
UndeTned
0x00000008
Software interrupt
Supervisor
0x0000000C
Abort (prefetch)
Abort
0x00000010
Abort (data)
Abort
0x00000014
-- reserved --
--
0x00000018
IRQ
IRQ
0x0000001C
FIQ
FIQ
Table 3: Vector Summary
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