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參數(shù)資料
| 型號(hào)： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器） |
| 文件頁數(shù)： | 17/121頁 |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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Programmer's Model
13
3.4 Exceptions
Exceptions arise whenever there is a need for the normal flow of program execution to be broken, so that
(for example) the processor can be diverted to handle an interrupt from a peripheral. The processor state
just prior to handling the exception must be preserved so that the original program can be resumed when
the exception routine has completed. Many exceptions may arise at the same time.
ARM60 handles exceptions by making use of the banked registers to save state. The old PC and CPSR
contents are copied into the appropriate R14 and SPSR and the PC and mode bits in the CPSR bits are forced
to a value which depends on the exception. Interrupt disable flags are set where required to prevent
otherwise unmanageable nestings of exceptions. In the case of a re-entrant interrupt handler, R14 and the
SPSR should be saved onto a stack in main memory before re-enabling the interrupt; when transferring the
SPSR register to and from a stack, it is important to transfer the whole 32 bit value, and not just the flag or
control fields. When multiple exceptions arise simultaneously, a fixed priority determines the order in
which they are handled. The priorities are listed later in this chapter.
3.4.1 FIQ
The FIQ (Fast Interrupt reQuest) exception is externally generated by taking the
input can accept asynchronous transitions, and is delayed by one clock cycle for synchronisation before it
can affect the processor execution flow. It is designed to support a data transfer or channel process, and has
sufficient private registers to remove the need for register saving in such applications (thus minimising the
overhead of context switching). The FIQ exception may be disabled by setting the F flag in the CPSR (but
note that this is not possible from User mode). If the F flag is clear, ARM60 checks for a LOW level on the
output of the FIQ synchroniser at the end of each instruction.
nFIQ
input LOW. This
When a FIQ is detected, ARM60 performs the following:
(1)
Saves the address of the next instruction to be executed plus 4 in R14_fiq; saves CPSR in SPSR_fiq
(2)
Forces M[4:0]=10001 (FIQ mode) and sets the F and I bits in the CPSR
(3)
Forces the PC to fetch the next instruction from address 0x1C
To return normally from FIQ, use SUBS PC, R14_fiq,#4 which will restore both the PC (from R14) and the
CPSR (from SPSR_fiq) and resume execution of the interrupted code. R14_fiq is a symbol for the register
R14 and if used needs to be declared in the users application program.
3.4.2 IRQ
The IRQ (Interrupt ReQuest) exception is a normal interrupt caused by a LOW level on the
has a lower priority than FIQ, and is masked out when a FIQ sequence is entered. Its effect may be masked
out at any time by setting the I bit in the CPSR (but note that this is not possible from User mode). If the I
flag is clear, ARM60 checks for a LOW level on the output of the IRQ synchroniser at the end of each
instruction. When an IRQ is detected, ARM60 performs the following:
nIRQ
input. It
(1)
Saves the address of the next instruction to be executed plus 4 in R14_irq; saves CPSR in SPSR_irq
(2)
Forces M[4:0]=10010 (IRQ mode) and sets the I bit in the CPSR
(3)
Forces the PC to fetch the next instruction from address 0x18
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