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參數(shù)資料
| 型號： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡指令集微處理器） |
| 文件頁數(shù)： | 30/121頁 |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
26
Figure 11: Logical Shift Right
The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32,
which has a zero result with bit 31 of Rm as the carry output. Logical shift right zero is redundant as it is
the same as logical shift left zero, so the assembler will convert LSR #0 (and ASR #0 and ROR #0) into LSL
#0, and allow LSR #32 to be specified.
An arithmetic shift right (ASR) is similar to logical shift right, except that the high bits are filled with bit 31
of Rm instead of zeros. This preserves the sign in 2's complement notation. For example, ASR #5 is shown
in
Figure 12: Arithmetic Shift Right
.
Figure 12: Arithmetic Shift Right
The form of the shift field which might be expected to give ASR #0 is used to encode ASR #32. Bit 31 of Rm
is again used as the carry output, and each bit of operand 2 is also equal to bit 31 of Rm. The result is
therefore all ones or all zeros, according to the value of bit 31 of Rm.
Rotate right (ROR) operations reuse the bits which 'overshoot' in a logical shift right operation by
reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right
operations. For example, ROR #5 is shown in
Figure 13: Rotate Right
.
contents of Rm
value of operand 2
31
0
carry out
0 0 0 0 0
5
4
contents of Rm
value of operand 2
31
0
carry out
5
4
30
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