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參數(shù)資料
| 型號： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡指令集微處理器） |
| 文件頁數(shù)： | 48/121頁 |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
44
Figure 22: Pre-decrement addressing
4.8.4 Use of the S bit
When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer
list and on the type of instruction. The S bit should only be set if the instruction is to execute in a privileged
mode.
LDM with R15 in transfer list and S bit set (Mode changes)
If the instruction is a LDM then SPSR_<mode> is transferred to CPSR at the same time as R15 is loaded.
STM with R15 in transfer list and S bit set (User bank transfer)
The registers transferred are taken from the User bank rather than the bank corresponding to the current
mode. This is useful for saving the user state on process switches. Base write-back shall not be used when
this mechanism is employed.
R15 not in list and S bit set (User bank transfer)
For both LDM and STM instructions, the User bank registers are transferred rather than the register bank
corresponding to the current mode. This is useful for saving the user state on process switches. Base write-
back shall not be used when this mechanism is employed.
When the instruction is LDM, care must be taken not to read from a banked register during the following
cycle (inserting a NOP after the LDM will ensure safety).
0x100C
0x1000
0x0FF4
Rn
1
0x100C
0x1000
0x0FF4
2
R1
0x100C
0x1000
0x0FF4
3
0x100C
0x1000
0x0FF4
4
R1
R7
R5
R1
R5
Rn
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