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| 型號(hào)： | ARM60 |
| 廠商： | Mitel Networks Corporation |
| 英文描述： | Low Power General Purpose 32-Bit RISC Microprocessor(低功耗通用32位精簡(jiǎn)指令集微處理器) |
| 中文描述： | 低功耗通用32位RISC微處理器（低功耗通用32位精簡(jiǎn)指令集微處理器） |
| 文件頁(yè)數(shù)： | 18/121頁(yè) |
| 文件大?。?/td> | 1217K |
| 代理商： | ARM60 |
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P60ARM-B
14
To return normally from IRQ, use SUBS PC,R14_irq,#4 which will restore both the PC and the CPSR and
resume execution of the interrupted code. R14_fiq is a symbol for the register R14 and if used needs to be
declared in the users application program.
3.4.3 Abort
An
access cannot be completed. For instance, in a virtual memory system the data corresponding to the current
address may have been moved out of memory onto a disc, and considerable processor activity may be
required to recover the data before the access can be performed successfully. ARM60 checks for ABORT
during memory access cycles. When successfully
aborted ARM60 will respond in one of two ways:
ABORT can be signalled by the external
ABORT
input. ABORT indicates that the current memory
(1)
If the
marked as invalid but the
executed, for example as a result of a branch being taken while it is in the pipeline, no
occur. An
abort will take place if the instruction reaches the head of the pipeline and is about to be
executed.
abort occurred during an instruction prefetch (a
abort exception does not occur immediately. If the instruction is not
Prefetch
Abort
), the prefetched instruction is
abort will
(2)
If the
abort occurred during a data access (a
Dat
a
Abort
), the action depends on the instruction type.
(a) Single data transfer instructions (LDR, STR) are
if the processor is configured for Early
are able to write back modified base registers and the Abort handler must be aware of this.
aborted as though the instruction had not executed
Abort. When configured for Late
Abort, these instructions
(b) The swap instruction (SWP) is
access may take place.
aborted as though it had not executed, though externally the read
(c) Block data transfer instructions (LDM, STM) complete, and if write-back is set, the base is updated.
If the instruction would normally have overwritten the base with data (i.e. LDM with the base in
the transfer list), this overwriting is prevented. All register overwriting is prevented after the
is indicated, which means in particular that R15 (which is always last to be transferred) is preserved
in an aborted LDM instruction.
Abort
When either a prefetch or data abort occurs, ARM60 performs the following:
(1)
Saves the address of the
R14_abt; saves CPSR in SPSR_abt.
aborted instruction plus 4 (for prefetch
aborts) or 8 (for data aborts) in
(2)
Forces M[4:0]=10111 (Abort mode) and sets the I bit in the CPSR.
(3)
Forces the PC to fetch the next instruction from either address 0x0C (prefetch abort) or address 0x10
(data
abort).
To return after fixing the reason for the
PC,R14_abt,#8 (for a data abort). This will restore both the PC and the CPSR and retry the
instruction. R14_fiq is a symbol for the register R14 and if used needs to be declared in the users application
program.
abort, use SUBS PC,R14_abt,#4 (for a prefetch
abort) or SUBS
aborted
The
memory management software is available. The processor is allowed to generate arbitrary addresses, and
when the data at an address is unavailable the MMU signals an
abort mechanism allows a
demand paged virtual memory system
to be implemented when suitable
abort. The processor traps into system
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