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參數(shù)資料
| 型號(hào)： | AM79C850KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 69/97頁 |
| 文件大小： | 358K |
| 代理商： | AM79C850KCW |
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P R E L I M I N A R Y
AMD
69
SUPERNET 3
SUPERNET 3 REGISTERS
SUPERNET 3 Programmable Registers
Register
Mnemonic
NPADDR7–0
Description
“cmdreg1”
“00”
Load the Command register 1 instruction
“cmdreg2”
“01”
Load the Command register 2 instruction
“st1u”
“00”
Upper 16 bits of status register 1 (Read Only)
“st1l”
“01”
Lower 16 bits of status register 1 (Read Only)
“st2u”
“02”
Upper 16 bits of status register 2 (Read Only)
“st2l”
“03”
Lower 16 bits of status register 2 (Read Only)
“imsk1u”
“04”
Upper 16 bits of IMSK register 1
“imsk1l”
“05”
Lower 16 bits of IMSK register 1
“imsk2u”
“06”
Upper 16 bits of IMSK register 2
“imsk2l”
“07”
Lower 16 bits of IMSK register 2
“said”
“08”
Short Address—individual
“l(fā)aim”
“09”
Long Address, individual (MSW of LAID)
“l(fā)aic”
“0a”
Long Address, individual (middle of LAID)
“l(fā)ail”
“0b”
Long Address, individual (LSW of LAID)
“sagp”
“0c”
Short Address—group
“l(fā)agm”
“0d”
Long Address, group (MSW of LAGP)
“l(fā)agc”
“0e”
Long Address, group (middle of LAGP)
“l(fā)agl”
“0f”
Long Address, group (LSW of LAGP)
“mod1”
“10”
Mode Register 1
“stmchn”
“11”
State Machine register
“mir1”
“12”
Upper 16 bits—MAC information register (Read Only)
“mir0”
“13”
Lower 16 bits—MAC information register (Read Only)
“tmax”
“14”
TMAX register
“tvx”
“15”
TVX register
“trt”
“16”
Upper 16 bits of TRT timer
“tht”
“17”
Upper 16 bits of THT timer
“tneg”
“18”
Upper 16 bits of TNEG register
“tmrs”
“19”
Lower 5 bits of TNEG, TRT, THT timers
Bit 14–10—Lower 5 bits of TNEG
Bit 9–5—Lower 5 bits of TRT
Bit 4–0—Lower THT timer
Bit 15 is the Late Count
“treq0”
“1a”
Station’s LSW of requested TRT
“treq1”
“1b”
Station’s MSW of requested TRT
“pri0”
“1c”
Priority register for ASYNC0
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