- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄366549 > AM79C850KCW (ADVANCED MICRO DEVICES INC) SUPERNET-R 3 PDF資料下載
參數(shù)資料
| 型號： | AM79C850KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 23/97頁 |
| 文件大?。?/td> | 358K |
| 代理商： | AM79C850KCW |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
P R E L I M I N A R Y
AMD
23
SUPERNET 3
Transmit Queues
ASYNC2 Transmit Queue Not Supported
The SUPERNET 3 supports SYNCHRONOUS, and two
ASYNCHRONOUS priorities. The ASYNC2 queue is no
longer supported. This causes the following changes:
1. TPRI2 (16-bit priority register for asynchronous
queue 2) is no longer implemented.
2. EAA2, WPXA2, SWPXA2, RPXA2 registers are no
longer implemented.
3. The ‘Clear Asynchronous Queue 2 Lock’ and
‘Transmit Asynchronous Queue 2’ commands are
no longer available in the command registers 1 and
2, respectively. The value 0x18 in command register
1 and 0x08 in command register 2 shall not be
decoded to any other instruction. These values are
reserved.
4. The STEFRMA2, STECFRMA2 and STXABRA2
bits in the upper 16 bits of the status register 1
(ST1U) are reserved and set to zero. Similarly
SQLCK2, STXINFLA2, SPCEPDA2, and STBURA2
are reserved and set to zero.
5. The QCTRL[2:0] = 100 encoding is now invalid. This
encoding
indicated
Asynchronous Queue 2’ which is no longer
available. The encoding is reserved and shall not be
used to indicate any other QCTRL condition. (See
NOTE)
‘Request
transfer
into
6. The HSREQ[2:0] = 111 is now decoded as “Write
Request: Asynchronous Queue 1”. In FORMAC+
this request indicated a write request to
asynchronous queue 2 which is no longer available.
Note:
If the encoding HSREQ[2:0] = 111 is used, the
SUPERNET 3 would not use the QCTRL[2:0] = 100
encoding to ndicate status of Asynchronous Queue, but
instead the QCTRL[2:0] = 011 (“Request transfer into
Asynchronous Queue 1”) encoding would be indicated
by SUPERNET 3 and external logic could be added to
invert this encoding to be compatible with FORMAC+.
AFULL Encoding of QCTRL Signals Modified
The QCTRL2–0 pins provide the encoded status of the
buffer memory transmit queues. The value QCTRL[2:0]
= 111, ‘Current queue almost full’, was asserted for one
host write cycle in SUPERNET 2. This signal shall now
be generated for every host write cycle until the queue
becomes full or the almost full threshold is no
longer exceeded.
This new signal assertion is implemented only if the bit
MENAFULL is set in mode register 3 (MDREG3)
Transmit Frame Format
In SUPERNET 2 transmit frames must consist of
aligned data, i.e. all words in the buffer memory must
contain four valid bytes, except that the last data word
may consist of less than four bytes. This required that
the Frame Control (FC) of the frame be written as the
most significant byte of the frame data long word.
SUPERNET 3 would support an enhanced feature,
where in the Frame Control (FC) could be any byte of the
frame data long word. The Destination Address (DA)
would follow the FC as the next byte in any mode of
operation. This feature is enabled only when the bits
MENFCLOC (bit 12 & 13) is set in mode register 3
(MDREG3). Upon reset these bits would be both zero
and the Frame Control (FC) has to be written as the
most significant byte of the frame data long word. The
following table describes the decoding of the
MENFCLOC bits in the mode register 3 (MDREG 3):
If MENFCLOC 13-12 = 00
01
10
11
Case 1: LSB = 0
Then FC starts at:
Byte 1
Byte 2
Byte 3
Byte 4
(MDREG 2 bit 11)
(MSBYTE)
(LSBYTE)
Case 1: LSB = 1
Then FC starts at:
Byte 4
Byte 3
Byte 2
Byte 1
(MDREG 2 bit 11)
(MSBYTE)
(LSBYTE)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AM79C864AKC | Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKCW | Physical Layer Controller With Scrambler (PLC-S) |
| AM79C873 | NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
| AM79C873KCW | NetPHY⑩ -1 10/100 Mbps Ethernet Physical Layer Single-Chip Transceiver with 100BASE-FX Support |
| AM79C874VI | NetPHY-1LP Low Power 10/100-TX/FX Ethernet Transceiver |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AM79C864A | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKC | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864AKCW | 制造商:AMD 制造商全稱:Advanced Micro Devices 功能描述:Physical Layer Controller With Scrambler (PLC-S) |
| AM79C864KC | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
| AM79C870KC/W | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:LAN Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。