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參數(shù)資料
| 型號： | AM79C850KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁數(shù)： | 17/97頁 |
| 文件大?。?/td> | 358K |
| 代理商： | AM79C850KCW |
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P R E L I M I N A R Y
AMD
17
SUPERNET 3
RS5–0
Receive Status (TTL output, high impedance)
The receive-status (RS4–0) pins indicate the type of
frame received, and the condition of the receive state
machine. The RS4–0 status output pins are encoded as
illustrated in Table 3 in the SUPERNET 2 data book and
the enhancements RS5–0 are described here.
RS5
RS4
RS3
RS2
RS1
RS0
Indicated Status
0
X
X
X
X
X
As in SUPERNET 2 FORMAC Plus
1
0
0
0
0
0
Reserved
1
0
X
0
0
1
Starting Delimiter and non-data
symbol received
OSM mode: Stripping frame
1
0
0
0
1
0
1
0
0
0
1
1
Reserved
1
0
0
1
0
0
Reserved
1
0
0
1
0
1
Frame Abort
1
0
0
1
1
0
Frame Flush
1
0
0
1
1
1
Reserved
through
1
1
1
1
1
1
Reserved
XS3–0
Transmit Status (TTL output, high impedance)
The transmit-status (XS3–0) pins indicate the transmit
status conditions of the MAC and are valid for one clock
cycle. These status signals are not present for repeated
or stripped frames. These status output pins are en-
coded as illustrated in Table 4 (SUPERNET 2 data
book) and the enhancements are described here.
XS3
0
0
0
0
0
XS2
0
0
0
0
1
XS1
0
0
1
1
0
XS0
0
1
0
1
0
Indicated Status
Quiescent.
Transmit Aborted.
Token Issued
Reserved.
Transmitting Syn-
chronous Queue.
Transmitting Asyn-
chronous Queue 0.
Transmitting Asyn-
chronous Queue 1.
Reserved
Reserved
Initiated Claim.
Initiated Beacon.
Initiated Void
MAC Frame
Aborted
Void Frame
Aborted
0
1
0
1
0
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
XDAMAT
External Destination Address Match (TTL input,
active low)
This input provides a means for additional destination-
address detection external to the SUPERNET 3. This
pin should be tied high when external destination-ad-
dress detection is not used. This input should remain
asserted for at least one BCLK cycle, and must be
deasserted for at least one BCLK cycle before a
subsequent external destination address match
is recognized.
The
XDAMAT
pin which is generated by the external AF
is logically ORed with the “af_da” output signal gener-
ated by the internal AF logic. This pin should be tied high
when external address detection (such as an external
AF) is not used.
XDA_XACT
External Destination Address Exact Match
(TTL input, active low)
This input indicates whether the external address match
was exact (low) or inexact (high). This input should
remain asserted for at least one BCLK cycle, and must
be deasserted for at least one BCLK cycle before a
subsequent external source address match is recog-
nized. It must be asserted and deasserted in an identical
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