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參數(shù)資料
| 型號(hào)： | AM79C850KCW |
| 廠商： | ADVANCED MICRO DEVICES INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SUPERNET-R 3 |
| 中文描述： | 1 CHANNEL(S), 100M bps, FDDI CONTROLLER, PQFP208 |
| 封裝： | PLASTIC, QFP-208 |
| 文件頁(yè)數(shù)： | 56/97頁(yè) |
| 文件大?。?/td> | 358K |
| 代理商： | AM79C850KCW |
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AMD
P R E L I M I N A R Y
56
SUPERNET 3
LSB
MSB
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
19574A-23
AFCOMP(0)
AFCOMP(1)
AFCOMP(2)
AFCOMP(3)
AFCOMP(4)
AFCOMP(5)
AFCOMP(6)
AFCOMP(7)
AFCOMP(8)
AFCOMP(9)
AFCOMP(10)
AFCOMP(11)
AFCOMP(12)
AFCOMP(13)
AFCOMP(14)
AFCOMP(15)
Figure 22. Node Processor Comparand Register (AFCOMP0)
Mask Registers (AFMASK2:0)
The mask registers are 16-bit registers that may be read
and written by the node processor. AFMASK0 corre-
sponds to bits 15:0 of the CAM mask entry. AFMASK1
corresponds to bits 31:16 of the CAM mask entry.
AFMASK2 corresponds to bits 47:32 of the CAM mask
entry. A “1” written to a bit position in the mask register
will enable the corresponding bit in the comparand to
participate in the comparison operation. A “0” written to
a bit in the mask register will disable, or mask, the
corresponding bit in the comparand. A bit that is masked
will always match the corresponding bit in a comparison
operation. This register will be cleared (filled with
zeroes) on a reset and will retain its data after each time
it is written until the next reset. This register will be
updated with the contents of the first matching entry in
the CAM if a “Read CAM” instruction is issued to the
command register while the FOUND bit is set.
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